
Intel looks At Creating A ‘Sub-Atom’ Chip Out Of India, renews focus on affordable PCs
Praveen Vishakantaiah, president of Intel India, said one innovation in the area of frugal engineering could soon be in…
Praveen Vishakantaiah, president of Intel India, said one innovation in the area of frugal engineering could soon be in…
Intel dominates the business of PC processors. But as consumers shift increasingly to tablets and smartphones, the comp…
There are plenty of really good, proven processor cores on the market today. But if you have more than simple control t…
The average base salary among the North American engineers surveyed totaled just over $100,000; annual compensation, in…
Femtocells are small, low power cellular base stations that extend coverage indoors where signals are weak. Broadcom Co…
We are in the fourth quarter and the outlook is cloudy for the rest of 2010 and heading into 2011. Here are some good …
A New York state agency plans to take over a technology park that houses the new 300-mm fab owned by U.S. silicon foun…
Is Intel preparing to push the issue with regard to its desire to move to 450-mm wafer sizes? One analyst thinks so . W…
Last week i was invited to a Tech Talk organized by Oracle India (Sun Microsystems BU). The title of the talk was "…
Infineon's Wireless Solutions unit has been working together with the Dresden design house "Blue Wonder" …
Today we are in the age of Digital Convergence seeing a major change in the way digital electronics systems are designe…
Hardware design specialist Libelium opens a new community site for electronics enthusiasts offering a wide range of tut…
In march we had an article covering the Italian project made to fill the gap between Embedded Low Cost and Wireless. T…
The topic of "peer code review" is a widely discussed topic in the context of design verification. I remember…
From the open forum that happened at Infineon today it was made clear that the carved out wireless division will be a s…
The Indian Institute of Science (IISc) and IITs, the premier engineering colleges of India, have earlier joined hands t…
Say YES for changing ONE light to LED at home. Get your organization to say YES to change ONE light per employee to LED…
As per the management email sent to Infineon employees this morning, Infineon and Intel have signed the contracts relat…
Linley Gwennap says "Making it clear that money is no object in its quest to become a major player in the smartph…
Our company today hosted a renowned motivational speaker Mr. John Foley of Blue Angels fame. The title of the talk be…
Infineon Technologies India Pvt Ltd has some openings for full time and contract positions. If you are interested in ap…
ip.access, the leading developer of femtocell and picocell solutions, and AlertMe.com, the pioneer in home energy mana…
The High Level Synthesis Blue Book is a comprehensive guide for designing hardware using C++. It is targeted to RTL…
This new model available in black or white from June 24 has an unchanged pricing at $199 for the 16GB model and $299 fo…
The conference schedule and the registration links can be found here . With a program that is focused on helping you de…
In this blog post, we will discuss some of the challenges and techniques involved in designing a clock network for a ve…
The objective here is to explore placement techniques which can lead to reduction in IR drop. One way to do this is to …
Clock skew variation estimation is an important topic in the design and analysis of high-performance digital circuits. …
How can you quantify the impact of dummy fill on post-layout timing? Dummy fill can be inserted into a layout using SO…
Whitespaces (empty space) are inserted in layouts in order to increase the routing resources of the chip. Have you ever…
Timing analysis inaccuracies due to crosstalk, multiple gate input switching, supply voltage variation, temperature, ma…
How do you observe and highlight the impact of assumptions on gate-length variability distributions (if any) on final d…
How do you quantify the effect of WireLength Models (WLM) and target frequency on the post-routing timing results?
Power gating adds enabling signals to a power supply network; dynamic power supply management adjusts supply voltage ac…
Constructing a zero-skew clock tree can be formulated as constructing a path-length balanced tree (assuming path delay …
Clock skew is a function of process variation, i.e., delay from the clock source to a leave of the clock tree is a stat…
Modern clock networks include several drivers in which delays are affected by the timing of their input signal transiti…
Re-timing reduces longest combinational logic paths by relocating some of the flip-flops, both logically and physically…
This is a process of combining several cells to form new library cells, and to optimize a transistor level netlist. Thi…
This task usually starts with a placed and routed design, then generating a transistor level netlist for it and further…
Process variation extraction needs to be design specific, and based on random field simulation, as mechanical engineeri…
Anuj, who's worked on video chips for nearly 20 years, is a great role model for all practicing engineers. He'…
Updated 28 Aug 2023: I have listed below a set of common interview questions asked mainly in interviews related to phys…
Here are five of the most insulting leadership practices , the ones that virtually guarantee a business will end up wi…
Q1: How would you speed up an ASIC design project by parallel computing? Which design stages can be distributed for pa…
Physicists at McGill University in the US now have a system where they can measure the energy involved in adding elect…
Each fall, the UW College of Engineering partners with the UW Alumni Association to present a series of free lectures …
With so much useful advise and talented career experts out there with often differing opinions, you will most likely en…