Timing
Probabilistic Timing Analysis
Because of shrinking feature sizes and the decreasing faithfulness of the manufacturing process to design features, pro…
Services
VLSI Career counselling request form
Based on the competency level of the applicants we reserve the right to offer a free service or charge a minimum admini…
3D Design
3D Integrated circuits
The semiconductor industry is struggling to maintain its momentum down the path of Moore’s Law, and it is becoming clea…
VN-Cover
EDA Tools - VN-Cover Emulator Coverage Analysis for HW Emulation
VN-Cover Emulator by TransEDA enables engineers to obtain coverage on their SoCs in a hardware-accelerated environment …
VN-Cover
EDA Tools - VN-Cover Coverage Analysis
VN-Cover by TransEDA is a code and FSM coverage tool that identifies any unverified parts of a simulated HDL design. VN…
Disclaimer
Copyright notice - Please read
The articles, publications and shared documents are included in this blog by the contributing authors as a mechanism t…
Verilog
Verilog and Specman 'e' Interview Questions
Question 1: Write a verilog assertion for the property that vector S of length 8 is always of even parity and the Hammi…
Phones
20 Cell phones with highest radiation levels
Cell phone radiation. Some consider it a heath-hazard of paramount importance. Others couldn't care less. Whichever…
Technology
GM Develops Augmented Reality Windshield
The entire windshield is turned into a transparent display to highlighting landmarks, obstacles and road edges on the w…
Top 25
Top 25 Chip ranking for 2009
ISuppli's final global revenue ranking for the top 25 semiconductor suppliers in 2009, in millions of U.S. dollars…
SystemC
SystemC AMS – A New Proposal For Mixed-Signal Verification
With increasing analog and mixed-signal content on systems-on-chip, design teams are looking for faster ways to run sys…
TechOnline
Logical and Physical Design Reuse
Electronics designs have become extremely complex and intricate, creating a need for software tools that support automa…
Interview Questions
Interview Questions - A startup in California
A communication device receives a clock up to X MHz. Write a verilog to verify that the clock meets this timing require…
Interview Questions
Logic Design Puzzle/Interview Question challenge
Consider the Boolean function F = ( x1 + x3 + x4 )(x2 + x3 + x4 )(x1 + x2 +x4)(x1 +x3 +x4)( x1 +x2 + x3 ). Find an…
Interview Questions
e Interview Question
Packets dispatched can be of 3 network types: atm, ieee or Ethernet. The packets have a Boolean flag field which indica…
TechOnline
Electronic System Level (ESL) Design using VaST tool
ESL design and verification is an emerging electronic design methodology that focuses on the higher abstraction level. …
TechOnline
FPGA Design Methods for Fast Turn Around
Today's FPGAs are doubling in capacity every 2 years and have already surpassed the 5 million equivalent ASIC gate …
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