Archive: March 2010

Probabilistic Timing Analysis for Process Variation

Because of shrinking feature sizes and the decreasing faithfulness of the manufacturing process to design features, process variation has been one of the constant themes of IC designers as new process nodes are introduced. This article reviews the problem and proposes a "probabilistic" approach as a solution to analysis and management of variability. Process variation may be new in the digital design framework, but it has long been t…

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VN-Cover Emulator: Coverage Analysis for Hardware Emulation

VN-Cover Emulator by TransEDA enables engineers to obtain coverage on their SoCs in a hardware-accelerated environment and reach a level of confidence similar to that achieved using VN-Cover with software simulators. Using VN-Cover Emulator speeds up the overall verification task by providing better visibility on what has been covered, what is left, and when to stop verification. Key Features: * Coverage for statement, branch, toggle and…

VN-Cover: Code and FSM Coverage Analysis by TransEDA

VN-Cover by TransEDA is a code and FSM coverage tool that identifies any unverified parts of a simulated HDL design. VN-Cover includes a comprehensive set of metrics, which include line, statement, branch, condition, path, toggle, triggering, signal trace and FSM state, arc and path. In addition, the tool offers advanced features such as Deglitch and Coverability Analysis option, aimed at increasing measured coverage accuracy. VN-Cover seamles…

Verilog and Specman e Interview Questions: Assertions and Arbiters

Question 1: Write a verilog assertion for the property that vector S of length 8 is always of even parity and the Hamming distance among its feasible values is 2. (Hamming distance between two values is the number of bits in which the two values differ). Question 2: There are two bus masters linked to a central arbiter by individual request (REQ#) and grant (GNT#) signals. Each master has its own REQ# and GNT# lines. Apart from this the arbit…

20 Cell Phones with the Highest Radiation Levels (2010)

Cell phone radiation. Some consider it a heath-hazard of paramount importance. Others couldn't care less. Whichever camp you're in, there's some perverse satisfaction in clicking through CNET's countdown to see which is the most mind-melting gadget on the market.

GM Develops an Augmented Reality Windshield (2010)

The entire windshield is turned into a transparent display to highlighting landmarks, obstacles and road edges on the windshield in real-time. Such a system can point out to drivers potential hazards, such as a running animal, even in foggy or dark conditions, GM says. GM uses a special type of glass coated with red-emitting and blue-emitting phosphors--a clear synthetic material that glows when it is excited by ultraviolet light. The phosphor d…

Top 25 Semiconductor Suppliers Ranking for 2009 (iSuppli)

ISuppli's final global revenue ranking for the top 25 semiconductor suppliers in 2009, in millions of U.S. dollars (click on image to enlarge). Winners: AMD, Elpida, Hynix, IBM, MediaTek, Micron and Qualcomm. Losers: Freescale, Infineon, Marvell, NEC, NXP, Panasonic, Renesas, Rohm, Sharp and Sony. The winners climbed the IC rankings in 2009. The losers fell. Still, 2009 was a tough year for all. Out of approximately 300 semiconductor supp…

Logical and Physical Design Reuse

Electronics designs have become extremely complex and intricate, creating a need for software tools that support automation, maintain accuracy, and meet short design cycles. Re-using previously designed circuitry has long been an option for meeting these needs, but has never been easy to implement. Software providers have made attempts at providing this capability, but their solutions haven't always caught on. With new, more efficient option…

Interview Questions: Clock Frequency Checks and Functional Coverage

A communication device receives a clock up to X MHz. Write a verilog to verify that the clock meets this timing requirement. module ClockVerification;   // Input clock signal   reg clk;   // Specify the desired clock frequency in Hz   parameter desired_frequency = 10000000; // Example: 10 MHz   // Specify the tolerance for the clock frequency   parameter frequency_tolerance = 0.1; // 10% tolerance   // Time period for the desired clock frequency…

Logic Design Puzzle: Satisfying a Boolean Function Without SOP

Consider the Boolean function F = ( x1 + x3 + x4 )(x2 + x3 + x4 )(x1 + x2 +x4)(x1 +x3 +x4)( x1 +x2 + x3 ). Find an assignment of x1; x2; x3 and x4 that will make F=1. You are not allowed to transform the expression into any other form including SOP, K-Map etc. (a) Explain the strategy that you used clearly. (b) Write down the assignment to X. Write function F in Problem above in sum-of-products form. Find an assign-ment of x1; x2; x3 a…

Specman e Interview Question: Constrained Random Packet Generation

Packets dispatched can be of 3 network types: atm, ieee or Ethernet. The packets have a Boolean flag field which indicates whether the packet is "good" or "bad". The header of the packets is 32 bits in length. When the packet is atm, the entire header is randomly generated, but when it is ieee or Ethernet the lowest 4 bits are always zero. 20% of the time atm packets are generated, while remaining time ieee or Ethernet packet…

3G Modems Are a $3.5 Billion Market in 2010, Says In-Stat (2010)

Electronic System Level (ESL) Design Using the VaST Tool

ESL design and verification is an emerging electronic design methodology that focuses on the higher abstraction level. The basic essence is to model the behavior of the entire system using a high-level language such as C, C++, SystemC or SystemC TLM-2.0. ESL is evolving into a set of methodologies that enable embedded system design, hardware verification, debugging through to the hardware and software implementation of custom SoC, and Architectu…

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Magnetic Solder to Wire 3D Chips (2010)

A new type of solder can be melted and shaped in three dimensions under the force of a weak magnetic field. Using a magnet to pull the solder up through narrow holes makes it possible to create electrical connections between stacked silicon chips, for example. These three-dimensional chips pack more computing power in a given area, but making connections between them is expensive, a problem that the new solder might address. The solder also cont…

What Is the Destiny of the Semiconductor Industry?

Moore's Law continues to drive an inexorable increase in the number of transistors that can be integrated onto a single die. Chip architects continue to find ways to use all of these transistors to produce even more complex designs. At the same time, competitive pressures are dictating shorter design cycles and faster time to market, while design team size has reached (and perhaps exceeded) the limit beyond which further growth is impractica…

How to Spot Suspicious VoIP Signals

One way to steal data is to embed it in a voice call over the internet. Now network engineers are learning how to spot such attacks.ISo-called Voice of Internet Protocol or VoIP makes for cheaper and more convenient calling but it also opens an important issue of security. Various people have described how it might be possible to to hi-jack VoIP signals to send confidential information.Follow the link for more info.

Faster Optical Switching Through Chemistry (2010)

Specially designed molecules could lead to all-optical data switches that could make the Internet far faster. New molecules produced at Georgia Tech could enable engineers to build all-optical data routers, ultimately leading to transmission speeds as high as two terabits--or 2,000 gigabits--per second. Today's fastest commercial routers switch data at 40 gigabits per second. Follow the links for more info.

Making More Solar Cells from Silicon (2010)

A new manufacturing process could cut the cost of making crystalline silicon wafers for solar cells by 80 percent. The process is being developed by Lexington, MA-based 1366 Technologies , which this week showed off the first solar cells made this way. The technology is key to the company's plan to make solar power cheaper than the electricity generated from coal within 10 years. Follow the links for more info.

Hacked Roomba Builds a Searchable Index of Your House (2010)

Swedish hackers have put together the GåågleBot: 'a 'home crawler' consisting of a vacuum roomba with an on board webserver and camera. While the vacuum goes about its business, it extracts text from the images it takes. The text is later put in a database on the roomba and searchable through a web interface. Please follow the link for more info.

FabFi: Building High-Speed Wireless in Afghanistan from Scrap (2010)

Volunteers in Afghanistan -- both locals and foreigners from the MIT Bits and Atoms lab -- have been building out a wireless network made largely from locally scrounged junk. They call it 'FabFi' and it's kicking ass, especially when compared with the World Bank-funded alternative, which has spent seven years and hundreds of millions of dollars and only managed its first international link last summer.

Nokia Ovi Store Adds Skype for 3G and WiFi Phones (2010)

Attention all Nokia owners with 3G and WiFi connectivity: Today Nokia has added Skype to it Ovi arsena l and foreshadows death of regular phone calls! With all the benefits of Skype on your phone you can save money and stay in touch when you're on the move. You can make free Skype-to-Skype calls and IM on 3G or WiFi, Save money on calls and texts (SMS) to phones abroad, Share pictures, videos and other files from your phone. It's free to…

How to Inexpensively Design an ASIC in 5 Weeks

If you have ever designed a standard cell ASIC from scratch, you probably still have the scars to show for it. Designing a standard cell ASIC is not for the weak-hearted. A new generation of ASIC, (dubbed the NEW ASIC), is gaining momentum as an alternative to both standard cell ASIC and FPGA design which is explained in this paper . This new generation of ASIC combines the fast turnaround, low up-front development costs and simple design flow b…

Reduce Power, Area and Routing Congestion with an AXI Interconnect

This paper , using an example design, demonstrates how to meet challenging performance, latency and bandwidth goals by using the DesignWare Interconnect Fabric for the ARM AMBA 3 AXI while minimizing the total area, power consumption and number of top-level wires. The paper also studies the design requirements and examines the optimization features of the DesignWare Interconnect Fabric used to meet the stringent timing requirements. Detailed tec…