1394 Trade Association Issues Comprehensive FireWire Reference Tutorial for IEEE 1394 Standard

The 1394 Trade Association has developed a comprehensive new reference tutorial to assist engineers in evaluating the IEEE 1394 (FireWire) standard, understanding how it works, and maximizing FireWire performance in their applications. The tutorial provides a comprehensive technical background for engineers unfamiliar with FireWire, enabling them to build a complete understanding of how the standard operates, and to evaluate FireWire's benefits for their application. The 77-page document includes diagrams, descriptions and illustrations.

Dedicated sections discuss FireWire's use in a wide range of systems and applications including robotics control; automated optical inspection; medical imaging; computer and storage; audio and professional audio; security and surveillance; communications systems; set-top boxes; digital camcorders; commercial aviation; military and automotive. The tutorial also describes the most popular products including Host Adapters (Host Controllers); PC motherboards; cables; repeaters; IIDC cameras; external hard disks; digital cameras, camcorders and others.

Dimitrios Staikos of Codemost, Inc. authored the reference tutorial, with contributions from veteran 1394 Trade Association members Eric Anderson of Apple, Don Harwood of PLX Technology, Les Baxter of Baxter Enterprises and Burke Henehan, Henehan Consulting. Member companies such as Point Grey Research and IOI Technology Corp. contributed the photos used to explain applications.

"Our new Reference Tutorial presents a complete picture of what FireWire is, how it works, what designers need to evaluate its benefits for their application, and the steps they need to follow to optimize FireWire for their product," said Max Bassler, 1394 Trade Association chairman. "It has been developed specifically for engineers who have no previous experience with FireWire, based on the expertise developed by the dedicated designers and engineers in the Trade Association."

The new reference tutorial complements the 1394 Trade Association's newly-issued Design Guide, which details the guidelines for implementing FireWire ports on high level complex devices such as personal computers, automobiles and on simple devices such consumer electronics products. "The Design Guide and Reference Tutorial documents provide a comprehensive set of instructions, tools and guidelines for using 1394 in any product or application," Bassler said.

Probabilistic Timing Analysis

Because of shrinking feature sizes and the decreasing faithfulness of the manufacturing process to design features, process variation has been one of the constant themes of IC designers as new process nodes are introduced. This article reviews the problem and proposes a "probabilistic" approach as a solution to analysis and management of variability.

Process variation may be new in the digital design framework, but it has long been the principle worry of analog designers, known as mismatch. Regardless of its causes, variation can be global, where every chip from a lot can be effected in the same way, or quasi-global, where wafers or dies may show different electrical characteristics. Such global variation has been relatively easy to model, especially if process modeling people have been able to characterize it with a single "sigma" parameter. Timing analyzers need to analyze a design under both worst case and best case timing conditions. Usually, two extreme conditions of "sigma" sufficed to provide these two conditions. With the new process nodes , however, not only it is necessary to have several variational parameters, but individual device characteristics on a chip could differ independently, known as on-chip variation (OCV).

At the device level, process variation is modeled by a set of "random" parameters which modify the geometric parameters of the device and its model equations. Depending on the nature of the variation, these may effect all devices on the chip, or certain types of devices, or they may be specific to each instance of the device. Because of this OCV, it is important that correlation between various variational parameters be accounted for. For example, the same physical effect is likely to change the length and width of a device simultaneously. If this is ignored, we may be looking at very pessimistic variation scenarios.

There are some statistical methods which try to capture correlations and reduce them to a few independent variables. Some fabs use use parameters related to device geometries and model parameters. The number of such parameters may range from a few to tens, depending on the device. If one considers global and local variations, the number of variables quickly can get out of hand. Variation is statistically modeled by a distribution function, usually Gaussian. Given the value of a variational parameter, and a delta-interval around it, one can calculate the probability that the device/ process will be in that interval and will have specific electrical characteristics for that condition. Instead of having a specific value for a performance parameter such as delay, it will have a range of values with specific probabilities depending on the variational parameters.

To analyze the performance of digital designs, two approaches have emerged: statistical static timing analysis (SSTA) and multi-corner static timing analysis. SSTA tries to generate a probability distribution for a signal path from delay distributions of individual standard cells in the path. This is usually implemented by using variation-aware libraries, which contain a sampling of cell timing at various discrete values of the variational parameters. Because of the dependence on a discrete library, this approach is practically limited to only few global systematic variables, with a very coarse sampling of the variation space. Since it is a distribution-based analysis, it depends on the shape of primary variables. It is generally assumed these are Gaussian, but there is no reason to assume this. In fact, most process models may not even be centered. In addition, it becomes difficult to do input slope dependent-delay calculation. Assumptions and simplifications could quickly make this approach drift from the goal. Since it has the probability distributions, one can report a confidence level about a timing violation. Implicit in this approach is the assumption that any path has a finite probability of being critical.

Multi-corner timing analysis is kind of Monte-Carlo in disguise, and has been gaining popularity as a brute-force method. Someone who knows what he/she is doing decides on a set of extreme corner conditions. These are instances of process variables, and cell libraries are generated for these conditions. Timing analysis is performed using these libraries. The number of libraries may be 10 to 20 or more. Naturally, this approach is still limited to few global variational parameters. It is also difficult to ascertain the reliability of timing analysis, in terms of yield. The only way to increase the confidence level is by building more libraries and repeating the analysis with them. This process increases verification and analysis time, but does not guarantee coverage.

What we propose instead, is probabilistic timing analysis. It can address both global and local variations, and we can have a lower confidence limit on timing analysis results which can be controlled by the designer. This turns the problem upside down. Since timing analysis is interested in worst-case and best-case timing conditions of a chip, we ask the same question for individual cells making up a design. We want to find the best/ worst case timing condition of a cell. While doing this, we need to limit our search and design space. For example, the interval (-1,1) covers 68.268% of the area under the normal bell curve distribution. If we search this interval for sigma with maximum inverter delay and later use that value, we can only say that the probability that this value is the maximum delay is 0.68268. For the interval (-2,2), it is 0.95448. If we had searched a wider interval, our confidence level would go up even higher. If there were two process variables, and if we had searched (-1,1)(-1,1), our confidence would drop to 0.68268X0.68268, or 0.46605.

Although lower confidence limits are set by the initial search intervals, the actual probabilities may be much higher. If the maximum had occurred at extreme corners, one could expect that as the search interval expands, we might see new maximum conditions. On the other hand, if the maximum had occurred at a point away from the corners, most likely this is the absolute value. Typically, only one of the parameters, the one most tightly coupled to threshold voltage, for example, takes up the extreme values, and most others take intermediate values. In these cases it is effectively the same as if we searched the interval (-inf, +inf). This behavior is consistent with the traditional approach, where a single parameter is used to control best and worst timing corners.

One of the conceptual problem with our probabilistic approach is that each cell may have different sets of global variables, which contradicts the definition of such variables. A flip-flop may have different global variables than an inverter. Even inverters of different strengths may have different sets. They are typically close to each other, however. There may be some pessimism associated with this condition.

It is easy to establish confidence levels on critical path timing. If for example, global variables have a confidence level of 0.9, and local random variables have 0.95, the confidence level for a path of 10 cells is 0.9X0.95*10= 0.5349. Since local variations of each gate are independent of each other, intersection rule of probability should be followed, probability of having 0.95 coverage for two independent cells is 0.95X0.95, for three is 0.95X0.95X0.95, etc. In reality though, minimum and maximum conditions for local variations are clustered around the center, away from the interval end points, which brings confidence level to 0.9, confidence level for global variations. Alternatively, one can expand the search interval to cover more process space. Also keep in mind, the variation range of "real" random variables is much narrower than (-inf, +inf).

Library Technologies has implemented this probabilistic approach in its YieldOpt product. The user defines the confidence levels her/she would like to see, and identifies global and local random parameters for each device. Confidence levels are converted to variation intervals assuming a normal distribution. This is the only place we make an assumption about the shape of the distributions. As a result, our approach has a weak dependence on probability distribution. In the probabilistic approach, we view timing characteristics of a cell as functions of random process variables. For each variable, we define a search interval. The variables could be global and local random variables. Maximum and minimum timing conditions for each cell are determined for typical loads and input slopes. Two libraries are generated for each condition. Normally, we couple worst process condition with high temperature, low voltage; and best process condition with low temperature and high voltage.

Timing analysis flow is the traditional flow, and depending on the number of random variables, searching for extreme conditions becomes a very demanding task. We have developed methods and tools which can achieve this task in a deterministic way. The YieldOpt product determines appropriate process conditions for each cell and passes it over for characterization and library generation. Determining worst/best case conditions may add about 0.1X to 2X overhead on top of characterization.

By Mehmet Cirit:
Mehmet Cirit is the founder and president of Library Technologies, Inc. (LTI). LTI develops and markets tools for design re-optimization for speed and low power with on-the-fly cell library creation, cell/ memory characterization and modeling, circuit optimization, and process variation analysis tools such as YieldOpt.

Words of wisdom

Simulation cycle is the simulator step time i.e. a time value at which the clock in the design is being run like 10 ns, 200 ns, etc

Words of wisdom

Simulation – Involves execution of the user-defined processes that interact with each other and with the environment. This is done through event generation based on simulation time, and causing the appropriate effected processes to respond to those events. Synopsys/Scirocco uses 'scsim' and Xilinx/Modelsim uses 'vsim' as their simulation engine.

Words of wisdom

Elaboration – Involves flattening the hierarchical description of the design to produce a netlist of processes. Signals and variables are initialized. The resulting model is ready to be simulated. Synopsys/Scirocco uses 'scs' and Xilinx/Modelsim uses 'vcom' for elaboration.

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3D Integrated circuits

The semiconductor industry is struggling to maintain its momentum down the path of Moore’s Law, and it is becoming clear that in addition to scaling line widths and chip sizes downward, some form of 3D IC integration will be necessary to achieve the interconnection density, manufacturing yields and cost targets. By vertically stacking and interconnecting semiconductor layers (3D integration), as opposed to continuing to shrink line widths, chip designers have the potential to get around the limitations of geometric scaling; enable a significant increase in performance and reduction in power consumption through reduced signal paths; and achieve true cost reduction through the use of proven fabrication techniques that will increase yields.

The crucial processing technology elements for 3D IC integration include: 1) through silicon via (TSV) formation; 2) wafer thinning; and 3) scalable wafer-level bonding technologies with 3D interconnect for W2W (wafer-to-wafer) or D2W (die-to-wafer) fabrication processes. The semiconductor manufacturers who adopt the optimum combination of these technologies will be the ones who lead the industry to the next level of higher device performance and lower fabrication costs.

Even as device physicists continue to debate whether the physical limits of 2D scaling will be reached at the 22-nm node or somewhere beyond, the rest of the industry is recognizing the increasing practical and financial constraints being imposed by each new milestone on the technology roadmap.

EDA Tools - VN-Cover Emulator Coverage Analysis for HW Emulation

VN-Cover Emulator by TransEDA enables engineers to obtain coverage on their SoCs in a hardware-accelerated environment and reach a level of confidence similar to that achieved using VN-Cover with software simulators. Using VN-Cover Emulator speeds up the overall verification task by providing better visibility on what has been covered, what is left, and when to stop verification.

Key Features:

* Coverage for statement, branch, toggle and FSM state and arc
* Verilog, VHDL and mixed-language support
* Detailed code coverage reports and graphical display
* Automatic FSM extraction and analysis
* Support for Cadence Palladium and Cobalt, EVE Zebu, Mentor Graphics Celaro and Vstation, and Verisity Xtreme

EDA Tools - VN-Cover Coverage Analysis

VN-Cover by TransEDA is a code and FSM coverage tool that identifies any unverified parts of a simulated HDL design. VN-Cover includes a comprehensive set of metrics, which include line, statement, branch, condition, path, toggle, triggering, signal trace and FSM state, arc and path. In addition, the tool offers advanced features such as Deglitch and Coverability Analysis option, aimed at increasing measured coverage accuracy.

VN-Cover seamlessly works with all leading simulators to measure coverage on VHDL, Verilog, SystemVerilog and mixed-language designs. It is a vendor-neutral coverage tool that works across simulators, languages and platforms, and can be also utilized with hardware-accelerated verification environments.
Key Features:

* Verilog, VHDL and mixed-language support
* Detailed code coverage reports and graphical display
* Automatic FSM extraction and analysis
* Advanced and unique glitch filtering capability
* Post-simulation coverability analysis option and results filtering
* Test-suite optimization facility
* Multi-platform, multi-simulator availability

Words of wisdom

Delta cycles are used by the simulator to order events within a simulation cycle. A delta cycle has an infinitesimally small delay and it does not appear on the trace waveform produced for analysis.

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Verilog and Specman 'e' Interview Questions

Question 1: Write a verilog assertion for the property that vector S of length 8 is always of even parity and the Hamming distance among its feasible values is 2. (Hamming distance between two values is the number of bits in which the two values differ).

Question 2: There are two bus masters linked to a central arbiter by individual request (REQ#) and grant (GNT#) signals. Each master has its own REQ# and GNT# lines. Apart from this the arbiter also receives an input reset (RST#) signal.
Consider the following timing specification: Whenever the signal RST# is deasserted and in the next clock cycle REQ# is asserted, the GNT# signal is asserted after 3 clock cycles after the REQ# assertion and remains high for 7 clock cycles. Write an 'e' code snippet to check for the above specification. Add to your code an assertion to check that only one GNT# signal is asserted by the arbiter at an instant
of time.

Question 3: Write a verilog code to generate the clock waveform shown in the following figure. The fall and the rising transitions have 300 ps and 200 ps jitter respectively.fig.jpg

4G silicon powers Sprint, HTC phones

Qualcomm's Snapdragon processor based Sprint and HTC phones are out in the wild but these beasts are upscale phones that run on the Android operating system. We are talking about the latest 1GHz Snapdragon QSD8650 chip--used in the phones cited above--will be followed by a 1.3GHz processor, the QSD8650a, this according to Mark Frankel, vice president of product management at Qualcomm CDMA Technologies.Dont forget to checkout Qualcomm's 4G on Laptops!

openPICUS project officially takes off

This brand new device is an wireless stack and application development platform put into one. It is intended to be smart and low cost to allow ideas to crossover the labs walls and to enter the real market. openPICUS as a hardware platform offers to students an opportunity to experience in their thesis an interaction with iPhone and Android. The first 50 pcs of the starter kit will be shipped for FREE to those who contribute with the best ideas to the project. This project advocates OPEN HARDWARE philosophy from the draft phase.

The main characteristics:

CPU Microchip PIC 24F 16 bit 44 pins QFN 64K Flash 8K Ram)
Wireless (Bluetooth / Wi-Fi)
Power 5V or 3,3V
Main connections: UART, Digital Inputs, Digital Outputs, Analog Inputs, PWMs, SPI display, I2C
Connector: 26 Ways IDC header (male) suitable for TH mounting or flat cable
SMT: 26 Pins for direct soldering PICUS to a PCB

PICUS gives a possibility to upload software by a serial port (you do not need a Microchip programmer).
Bluetooth offers SPP, OBEX, Headset profiles.
Wi-Fi gives an access to the integrated webserver, TCP socket, embedded FTP and email clients.
We are planning to realize a visual development tool to enable using of PICUS even without any software experience.


PICUS will have a range of "nests": boards with several kinds of sensors and with or without a display where PICUS will perform the wireless part and the CORE Cpu, all in one.


openPICUS will be the core and the wireless part of Internet of things, sensors, wireless messaging, standard converters, home and industrial small automation and more.

Words of wisdom

To extend your phones battery life: All things being equal, the C.D.M.A. mobile standard uses more power than a G.S.M. network. If battery life is critical, you might want to consider G.S.M. as long as its coverage meets your needs.

Words of wisdom

Inertial Delay – Default delay type in VHDL. Used to model gates that do not propagate short pulses. Any signal with a pulse-width shorter than the specified delay time is rejected.

Words of wisdom

Transport Delay – Intended to model wiring delay. Simply delays the signal by specified delay time.

Words of wisdom

If a signal is updated with the same value it had in the previous simulation cycle, then it does not change, and therefore does not trigger processes to resume.

Register for MUSIC India now

MUSIC (Magma Users Summit on Integrated Circuits) is dedicated to providing an open forum for users to share and exchange ideas on how they use Magma solutions to meet the challenges of IC and SoC design. It's a great opportunity to learn, share and network with your peers. Register now to reserve your spot. This year's program covers a range of Magma software capabilities including library characterization, synthesis, placement and routing, floorplanning, power optimization and circuit simulation. Users will share useful tips on how to leverage Magma software to improve results, reduce power, minimize costs and increase productivity.

Words of wisdom

Combinational for-loops are usually synthesizable. They are often used to build a combinatorial circuit for each element of an array.

20 Cell phones with highest radiation levels

Cell phone radiation. Some consider it a heath-hazard of paramount importance. Others couldn't care less. Whichever camp you're in, there's some perverse satisfaction in clicking through CNET's countdown to see which is the most mind-melting gadget on the market.

GM Develops Augmented Reality Windshield

The entire windshield is turned into a transparent display to highlighting landmarks, obstacles and road edges on the windshield in real-time. Such a system can point out to drivers potential hazards, such as a running animal, even in foggy or dark conditions, GM says. GM uses a special type of glass coated with red-emitting and blue-emitting phosphors--a clear synthetic material that glows when it is excited by ultraviolet light. The phosphor display, created by SuperImaging, is activated by tiny, ultraviolet lasers bouncing off mirrors bundled near the windshield. Three cameras track a driver's head and eyes to determine where she is looking. [Via Technology Review]

IC Insights' capex rankings for 2010

IC Insights Inc. has raised its forecast for IC capital spending. The firm forecasts that 2010 spending will rebound and hit $40.7 billion, a 57 percent increase over 2009. This is up from its previous forecast of plus 45 percent. In 2009, capex fell 30 percent, it was noted. In 2011, IC capital spending is expected to reach $48.6 billion, up 20 percent over 2010, according to the firm. [Via EE Times]

Top 25 Chip ranking for 2009

ISuppli's final global revenue ranking for the top 25 semiconductor suppliers in 2009, in millions of U.S. dollars (click on image to enlarge). Winners: AMD, Elpida, Hynix, IBM, MediaTek, Micron and Qualcomm.Losers: Freescale, Infineon, Marvell, NEC, NXP, Panasonic, Renesas, Rohm, Sharp and Sony. The winners climbed the IC rankings in 2009. The losers fell. Still, 2009 was a tough year for all. Out of approximately 300 semiconductor suppliers measured by iSuppli Corp., two-thirds suffered falling revenues in 2009.[Via EE Times]

Firm buys Qimonda fab for $12 million

Richmond Semiconductor LLC has bought the former Qimonda fab in Sandston, Va. for $12 million, according to the Richmond Times-Dispatch.

SystemC AMS – A New Proposal For Mixed-Signal Verification

With increasing analog and mixed-signal content on systems-on-chip, design teams are looking for faster ways to run system-level simulations. They also need to incorporate mixed-signal functionality into system-level design and architectural exploration. Spice and Fast Spice are too slow for full-chip, top-level verification, and even languages like Verilog-AMS can pose a performance bottleneck. In this article by Richard Goering, he speaks about what SystemC AMS is about, refrerring to white papers on Linear signal flow (LSF), Electrical linear networks (ELN) and Timed data flow (TDF).

Words of wisdom

Clocked for-loops are not synthesizable, but are very useful in simulation, particularly to generate test vectors for test benches.

Logical and Physical Design Reuse

Electronics designs have become extremely complex and intricate, creating a need for software tools that support automation, maintain accuracy, and meet short design cycles. Re-using previously designed circuitry has long been an option for meeting these needs, but has never been easy to implement. Software providers have made attempts at providing this capability, but their solutions haven't always caught on. With new, more efficient options at hand, will customers see the value? Will they give it a try? This paperintroduces a methodology that can handle today's data-filled design content and still produce proper, reusable designs.

e Interview Question - Cadence

A dual port RAM (DPRAM) provides a common memory accessible to 2 processors that can be used to share and transmit data and system status between two processors.

Consider a DPRAM wrapper in verilog: dram(addr0, data0, addr1, data1). The dimension of the data bus is 1 bit and that of the address bus is 4 bits. The wrappers, written in verilog has tasks read_memory and write_memory which you can invoke from a top level testbench. We also have suitable wrappers for the verilog codes for a processor: cpu(busy,addr,data,control)

The control and busy bits are 1 bit each and the data and address are as that of the DPRAM. A block named TestnSet probes two processors P0 and P1 which
share a DPRAM. The processors are connected to port0 and port1 of a shared DPRAM (refer Fig). The block named TestnSet maintains two special 1 bit registers sreg0 and sreg1 and two 1 bit flag registers, flag0 and flag1.

If the control bit of P0 goes high with the address value as say A, then the content of the memory is brought to the sreg0 and flag0 is set high. If P1's control bit also goes high and address value is also A, then P1 busy should be high. Otherwise there is an error. Irrespective of what happens to P1, the sreg0 register will be checked and if the value is 0, the content of data0 bus will be written to the address A. If the sreg0 register is 1, no write takes place.

Write an e code to verify the block TestnSet. Access the necessary verilog codes using the wrappers provided. Please state any assumptions that you have made.

Interview Questions - A startup in California

1. A communication device receives a clock up to X MHz. Write a verilog code snippet to verify that the clock meets this timing requirement. (Hint: Use fork and join constructs)

2. Comment briefly on the following:
a) 100% functional coverage ensures that the design can have no bugs.
b) 100% code coverage guarantees that the test bench is very well written.

Logic Design Puzzle/Interview Question challenge

Consider the Boolean function F = (x1 + x3 + x4)(x2 + x3 + x4)(x1 +x2 +x4)(x1 +x3 +x4)(x1 +x2 + x3).
Find an assignment of x1; x2; x3 and x4 that will make F=1.
You are not allowed to transform the expression into any other form including SOP, K-Map etc.
(a) Explain the strategy that you used clearly.
(b) Write down the assignment to X.

Write function F in Problem above in sum-of-products form. Find an assign-ment of x1; x2; x3 and x4 that will make F=1. As before, no transformations are allowed.
(a) Explain the strategy that you used clearly.
(b) Write down the assignment to X.

Use the sum-of-products form of F that you found in Problem 2. Find an assignment of x1; x2; x3 and x4 that will make F=0.

Answer the following questions:
(a) Which assignment to F was easier, assignment done on the SOP or the POS form? Why?
(b) Which assignment to F was harder, assigning 1 to F in problem 2 or assigning 0 to F in problem 3? Why?
(c) Compare the di difficulty of Problem 1 and Problem 3.
(d) Are your solution strategies general enough for any F given to you?

e Interview Question

Packets dispatched can be of 3 network types: atm, ieee or Ethernet. The packets have a Boolean flag field which indicates whether the packet is "good" or "bad". The header of the packets is 32 bits in length. When the packet is atm, the entire header is randomly generated, but when it is ieee or Ethernet the lowest 4 bits are always zero. 20% of the time atm packets are generated, while remaining time ieee or Ethernet packets are generated uniformly. Model the above scenario using language e.

Words of wisdom

Spend the time up front to plan a good design on paper. Use dataflow diagrams and state machines to predict performance and area. Usually a block might appear to be sufficiently small and simple that you can go straight to RTL code. However, you will probably produce a more optimal design with less effort if you explore high-level optimizations with dataflow diagrams and state machines.

Top 10 Strategic Technologies 2010

3G modems are $3.5 billion market in 2010, says In-Stat

Chip profitability jumps to decade high

Words of wisdom

The phrases "behavioural model" and "structural model" are commonly used for "high-level models" and "synthesizable models". In most cases, what people call structural code contains both structural and behavioural code. The technically correct definition of a structural model is an HDL program that contains only component instantiations and generate statements.

Electronic System Level (ESL) Design using VaST tool

ESL design and verification is an emerging electronic design methodology that focuses on the higher abstraction level. The basic essence is to model the behavior of the entire system using a high-level language such as C, C++, SystemC or SystemC TLM-2.0. ESL is evolving into a set of methodologies that enable embedded system design, hardware verification, debugging through to the hardware and software implementation of custom SoC, and Architecture and Performance analysis as well. This paper discusses Electronic System Level (ESL) design and the methodologies and the tools associated with it.

FPGA Design Methods for Fast Turn Around

Today's FPGAs are doubling in capacity every 2 years and have already surpassed the 5 million equivalent ASIC gate mark. With designs of this magnitude, the need for fast flows has never been greater. At the same time, designers are seeking rapid feedback on their ASIC or FPGA designs by implementing quick prototypes or initial designs on FPGA-based boards. These prototypes or designs allow designers to start development, verification and debug of the design—in the context of system software and hardware—and also to fine tune algorithms in the design architecture. Quick and intuitive debug iterations to incorporate fixes are of great value. The ability to perform design updates that don't completely uproot all parts of the design that have already been verified is also a bonus! Whether the goal is aggressive performance or to get a working initial design or prototype on the board as quickly as possible, this paper provides information on traditional and new techniques that accelerate design and debug iterations.

Words of wisdom

Analysis – Synonymous with compiling VHDL programs. Analyzer performs the customary syntactical checks, code generation, compilation and places the resulting model in the default design library WORK. Synopsys/Scirocco uses 'vhdlan' for analysis and Xilinx/Modelsim uses 'vcom'

Words of wisdom

Transaction – It occurs on a signal when a new assignment has been made to the signal, but the value may not have changed. It is a time-value pair where the value represents a future value of the signal and time represents when the update happen.

Words of wisdom

Postponed in VHDL terminology is a synonym for some operating systems usage of ready, to describe a process that is ready to execute.

Words of wisdom

Clocked processes are sometimes called sequential processes. they should not be confused with sequential statements.

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Magnetic Solder to Wire 3-D Chips

A new type of solder can be melted and shaped in three dimensions under the force of a weak magnetic field. Using a magnet to pull the solder up through narrow holes makes it possible to create electrical connections between stacked silicon chips, for example. These three-dimensional chips pack more computing power in a given area, but making connections between them is expensive, a problem that the new solder might address. The solder also contains no lead, and it is stronger than other lead-free solders. {Via Technology review}

Being efficient while Working Remotely

I am sure many of you have worked off-site and telecommuted for employers using email, chat, and web-based collaboration apps. But working with people in different cities and time zones with minimal visual interaction presents a whole new set of challenges. While the tools available for working remotely are better than ever, it's how you use them that really counts. Constant and clear communication is the key to a good remote working relationship. Here are some best practices I've found for working remotely online.[Article Via Elaine, Qualcomm]

Words of wisdom

We can talk about the setup and hold time of a signal or of a storage device like flip-flop. For a storage device, the setup and hold times are requirements that it imposes upon all environments in which it operates. For an individual signal in a circuit, there is a setup and hold time, which is the amount of time that the signal is stable before and after a clock edge.

Silicon Nanophotonics to Make Your Gadgets Run Faster and Consume Less

IBM is replacing copper wiring with an avalanche of photons and electrons. They are now transmitting data streams between circuits at the nanophotonic level. Speed: 40Gbps. Power supply: Just 1.5 volts. The video in the title link explains how it works.The system is so fast and consumes so little because of electron avalanches: The receptor—called nanophotonic avalanche photodetector—catches the photon, which starts an electron chain reaction thanks to the properties of Germanium. What does this mean: Faster, smaller, and more power efficient devices. And the possibility of saying "nanophotonics" any time we want.

Words of wisdom

For a storage device like a flip-flop, the setup and hold times are requirements that the device imposes upon its environment. The clock-to-Q time is a guarantee. If the environment satisfies the setup and hold times, then the storage device guarantees that it will satisfy the clock-to-Q time.

What is the destiny of the semiconductor industry?

Moore's Law continues to drive an inexorable increase in the number of transistors that can be integrated onto a single die. Chip architects continue to find ways to use all of these transistors to produce even more complex designs. At the same time, competitive pressures are dictating shorter design cycles and faster time to market, while design team size has reached (and perhaps exceeded) the limit beyond which further growth is impracticable. Where are we heading?

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Blog - How to Spot Suspicious VoIP signals

One way to steal data is to embed it in a voice call over the internet. Now network engineers are learning how to spot such attacks.ISo-called Voice of Internet Protocol or VoIP makes for cheaper and more convenient calling but it also opens an important issue of security. Various people have described how it might be possible to to hi-jack VoIP signals to send confidential information.Follow the link for more info.

Faster Optical Switching Through Chemistry

Specially designed molecules could lead to all-optical data switches that could make the Internet far faster.
New molecules produced at Georgia Tech could enable engineers to build all-optical data routers, ultimately leading to transmission speeds as high as two terabits--or 2,000 gigabits--per second. Today's fastest commercial routers switch data at 40 gigabits per second. Follow the links for more info.

Making More Solar Cells from Silicon

A new manufacturing process could cut the cost of making crystalline silicon wafers for solar cells by 80 percent. The process is being developed by Lexington, MA-based 1366 Technologies, which this week showed off the first solar cells made this way. The technology is key to the company's plan to make solar power cheaper than the electricity generated from coal within 10 years. Follow the links for more info.

Bloggers Now Eligible For Press Passes In NYC

The New York City Police Department announced Tuesday that bloggers and others who publish on the Web will now be eligible for press credentials. The move comes as a result of a lawsuit filed in 2008 by three Web journalists who were denied press passes. Please follow the link for more info.

Chip market boom makes analyst hike forecast

Bruce Diesen, analyst with Carnegie ASA (Oslo, Norway), has raised his forecast for 2010 chip market growth from 13 percent to 15 percent on the strength of the January global chip sales reported by the SIA. Follow the link for more info.

Hacked Roomba will google your house

Swedish hackers have put together the GåågleBot: 'a 'home crawler' consisting of a vacuum roomba with an on board webserver and camera. While the vacuum goes about its business, it extracts text from the images it takes. The text is later put in a database on the roomba and searchable through a web interface. Please follow the link for more info.

Building high-speed wireless in Afghanistan out of garbage

Volunteers in Afghanistan -- both locals and foreigners from the MIT Bits and Atoms lab -- have been building out a wireless network made largely from locally scrounged junk. They call it 'FabFi' and it's kicking ass, especially when compared with the World Bank-funded alternative, which has spent seven years and hundreds of millions of dollars and only managed its first international link last summer.

Nokia Ovi store reveals Skype :-)

Attention all Nokia owners with 3G and WiFi connectivity: Today Nokia has added Skype to it Ovi arsenal and foreshadows death of regular phone calls! With all the benefits of Skype on your phone you can save money and stay in touch when you're on the move. You can make free Skype-to-Skype calls and IM on 3G or WiFi, Save money on calls and texts (SMS) to phones abroad, Share pictures, videos and other files from your phone. It's free to use Skype in a WiFi zone. If you use Skype with a mobile data connection, operator charges may apply.

How to Inexpensively Design an ASIC in 5 Weeks

If you have ever designed a standard cell ASIC from scratch, you probably still have the scars to show for it. Designing a standard cell ASIC is not for the weak-hearted. A new generation of ASIC, (dubbed the NEW ASIC), is gaining momentum as an alternative to both standard cell ASIC and FPGA design which is explained in this paper. This new generation of ASIC combines the fast turnaround, low up-front development costs and simple design flow benefits that are normally associated with FPGAs, with the low unit power consumption and cost approaching that of a standard cell ASIC.

Reduce Power, Area and Routing Congestion

This paper, using an example design, demonstrates how to meet challenging performance, latency and bandwidth goals by using the DesignWare Interconnect Fabric for the ARM AMBA 3 AXI while minimizing the total area, power consumption and number of top-level wires. The paper also studies the design requirements and examines the optimization features of the DesignWare Interconnect Fabric used to meet the stringent timing requirements. Detailed technical analysis is provided for the selected architecture, pipelining mode, arbitration scheme and the slave visibility feature employed to reach timing closure for the links with demanding performance requirements. Final results are presented based on the hybrid architecture of the DesignWare Interconnect Fabric used to optimize the infrastructure resulting in a reduction in area, power and routing congestion.

How System-Level Trade-Offs Drive Data Converter Decisions

For both analog-to"digital converters (ADC) and digital-to"analog converters (DAC), system-level specifications have a strong influence on several aspects of the converter's design, including conversion rate, resolution, power dissipation and silicon area. With a special emphasis on broadband wireless applications, this white paper reviews the design trade-offs ranging from the converter's sampling rate to the choice of single- or multiple-chip system partitioning. Understanding these choices enables chip architects and designers to optimize their systems in accordance with their particular constraints and the characteristics of the data converters.

Improve Product Quality and Reliability with In-System Diagnostics

Product quality and reliability are first-order design requirements for any product development. This document describes how quality and reliability can be dramatically improved with In-System Diagnostics. An overview is provided on common design verification and hardware validation challenges and how to overcome them with a single source solution.

How to Create a Touchless Slider for Human Interface Applications

Imagine being able to control electronics products at home and in the office, not with a direct touch but with the sweep of your hand. Advanced "touchless" human interface technology is now within the realm of practical implementation, even for products as commonplace as the alarm clock beside your bed. We all have experienced the frustration of locating the snooze and silence buttons on an incessantly beeping alarm clock at 6:00 a.m. What if you could extend your sleep just a bit longer by simply waving your hand or tapping a virtual button to shut off the alarm without fumbling to find the clock in the dark?