Testing
The Economics of Test, Part - IV
Detecting a defective unit is often only part of the job. Another important aspect of test economics that must be considered is the cost of ...
Showing posts from 2008
Testing
The Economics of Test, Part - III
However, if devices are tested, feature sizes can be reduced and more die will fit on each wafer. Even after the die are tested and defectiv...
I have something to explain
The Economics of Test, Part - II
The table depicted shows test cost broken down into four categories some of which are one-time, non recurring costs whereas others are recur...
I have something to explain
The Economics of Test, Part - I
What are the factors that influence the cost of test? Quality and test costs are related, but they are not inverse of one another. As we sha...
TCL for EDA
TCL for EDA - A repository Free TCL/TK tools, scripts for EDA...
http://www.tclforeda.org/ The TCL for EDA project is an open-source repository of TCL/TK tools, applications, scripts and methodological art...
Transport Delay
Transport delay / Inertial Delay / Delta Delay
In Verilog and VHDL, there are three types of delays that are commonly used in digital logic simulation: delta delay, transport delay, and...
Cycle Simulation
Cycle based simulation
New design starts continue to grow in gate count, and the amount of CPU time required to simulate these designs tends to grow disproportiona...
Event Driven Simulation
Event driven simulation/simulator
A latch or flip-flop does not always respond to activity on its inputs. If an enable or clock is inactive, changes at the data inputs have n...
Linting
Linting tools
Some of the tools used for design verification of ICs have their roots in software testing. Tools for software testing are sometimes charact...
White box testing
White box testing or Black box testing
When performing verification, the target device can be viewed as a white box or a black box. During whitebox testing, detailed knowledge is ...
Netlist
Formal Verification or EquivalenceChecking
Design verification, must show that the design, expressed at the RTL or structural level, implements the operations described in the data sh...
Interview Questions
Avago Technologies (former HP group) Interview Questions
How do you minimize clock skew/ balance clock tree? Given 11 minterms and asked to derive the logic function. Given C1= 10pf, C2=1pf conne...
Interview Questions
Hynix Semiconductor Interview Questions
How do you optimize power at various stages in the physical design flow? Power optimization is an important aspect of physical design, and t...
Interview Questions
Hughes Networks Interview Questions
What is setup/hold? What are setup and hold time impacts on timing? How will you fix setup and hold violations? Explain function of Muxed F...
Qualcomm
Qualcomm Interview Questions
RTL Design In work Design Verification In work Physical Design In building the timing constraints, do you need to constrain all IO (Input-Ou...
Interview Questions
Texas Instruments (TI) Interview Questions
How are timing constraints developed? Explain timing closure flow/methodology/issues/fixes. Explain SDF (Standard Delay Format) back annot...
Interview Questions
ST Microelectronics - Interview Questions
What were the challenges you faced in physical design, PAR (place and route), FV (Formal Verification)? What was the average design cycle t...
Interview Questions
Digital design interview questions
Search in this blog for all the available articles and resources! ------------------------------- PROMOTION -----------------------------...
Technical Leadership
The Great Divide – Technical Leadership and Project Management
[Via Coaching Excellence in IC Design Teams] This is bitterly true. Intel is one example of why it is #1.
Debates and Discussions
47 CEOs for Cadence
[Via Deepchip ] I feel even that baiting a big name CEO from EDA background, from the list will not help. This is more about the basics. The...
what will work
Unit delay simulation - an intermediate step in Gate level simulation!
This is an intermediate step during Gate level simulation! Unit delay simulation operates on the assumption that all the elements in a circu...
what will work
Different types of simulations!
Functional simulation : Simulation of a design description. This is also called spec simulation or concept simulation. This is usually done ...
Search
Get your Blog listed in our Google Custom Search Engine
To get your Blog listed in our Google Custom Search Engine please send us an e-mail with your Blog details to onenanometer [at] gmail [dot] ...
Self Esteem
Performance-Contingent Self Esteem
Don't be too committed in your profession where you reach a point where it might boomerang, leaving you depressed, anxious and fretful, ...
Terrorism
Mumbai Terror!
If you want to get in touch with your loved one in Mumbai... follow this link http://mumbaiterrorhelpline.blogspot.com/ List of Injured and ...
Interview Questions
Digital Logic Design - Interview Essentials!
Hello Readers, Due to the recent spate of Layoffs , a high amount of panic and interview preparation frenzy has seeped into the industry. T...
VLSI
What Users Would Change About This Blog!
The best part about this survey is that you get to see what users are looking for, whats bothering them that they would like it changed and ...
VLSI Conference
Layoff Watch!
Announced Worldwide Layoffs As of 30th January 2009 Infineon - 3000 Qimonda - 3000 (Bankrupt: 23 Jan 09) Renesas - 150 ST - 4500 (Upda...
Investments
Intel will invest through recession!
Intel will continue to invest in products and technologies even though it sees that a U.S.financial meltdown is likely to affect the emergin...
Wireless
10 Gbps Wireless
Engineers at Battelle have come up with a way to send data through the air at 10 Gigabits per second using point-to-point millimeter-wave t...
Questions
VLSI Blogs
Based on the content and articles in this blog do you really think that this blog should be categorized under VLSI or ASIC or Chip design or...
Links
How to get a free link to your ASIC or VLSI Blog?
This is how you can get a free link to your blog. If you are not already a member of the ASIC/VLSI/Digital Electronics blogging community, j...
Forecats
Semiconductor forecast looks grim!
According to IC insights , the maket forecast looks grim for 2008 total worldwide IC market growth, noting shrinking demand from fabless sup...
XVGA
Simple XVGA (1024x768) Controller in Verilog
module xvga(clk,hcount,vcount,hsync,vsync); input clk; // 64.8 Mhz output [10:0] hcount; output [9:0] vcount; output hsync, vsync;...
References
Coaching Excellence in IC Design Teams: Why Can't we get Rid of that Thorn in our Process?
Coaching Excellence in IC Design Teams: Why Can't we get Rid of that Thorn in our Process? Commenting on this article by Jorvig... It is...
Jobs
Invitation to Freshers!
Infineon India - Bangalore is planning for a Fresher's Event in September 08 & thereby invites CVs of friends whose association with...