Displaying posts in the categoryASIC Design
ASIC Design articles
Tutorials
An ASIC (application-specific integrated circuit) and an SoC (system on chip) go through the same broad design flow, from specification to production, but an SoC takes roughly twice as long. In the infographic below, a focused ASIC runs about 12 to 24 months from specification to production, while a large SoC runs about 24 to 48 months. The extra time comes from integration: an SoC combines CPUs, GPUs, memory, licensed IP and software, and every…
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Murugavel Ganesan
March 04, 2026
SoC Design
In chip and system design, PPA (performance, power and area) are the three numbers every team argues about. You can usually improve any one of them, but almost never without paying for it in the other two. Image: SemiWiki The catch is that the best chip on paper is not always the best product in the market. From ADAS processors to AI accelerators, a PPA trade-off is a business decision as much as an engineering one. The wrong choice can hu…
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Murugavel Ganesan
July 08, 2025
Verification
A chip design house does not run the fab, but it controls most of what decides whether a chip survives tape-out, production and the field: how thoroughly the RTL is verified before tape-out, how manufacturable the layout is, how carefully third-party IP is qualified, and whether timing and behaviour are signed off across every process, voltage and temperature corner. Get those four right and most re-spins, yield losses and field failures are pre…
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Murugavel Ganesan
May 09, 2025
Tutorials
Your first hardware design will probably fail in the field because it was proven under lab conditions: stable supply, room temperature, short test runs and well-behaved neighbours. The field adds supply transients, heat, vibration, ageing, noisy partner devices and years of run time, and it exposes every state, register and corner case the design never planned for. You prevent most of these failures by designing for recovery, for observability a…
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Murugavel Ganesan
May 03, 2025
Top10
The RTL coding mistakes that cost the most power and area are the ones that make logic toggle when it does no useful work, or that build more hardware than the function needs. Clocks that run when registers hold their value, glitchy deep logic, oversized buses, resets on every flop and accidental latches are the usual culprits. Synthesis tools recover some of this, but they cannot undo an architecture or coding style that asks for waste. Below a…
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Murugavel Ganesan
April 07, 2025
Top 50
Design for Test (DFT) interviews test whether you understand how a chip is made testable after manufacture: scan insertion, fault models, ATPG, test compression, boundary scan, memory and logic BIST, and how coverage turns into shipped quality. The 50 questions below are the ones that come up most often, each with a short model answer you can build on. Interviewers rarely want definitions alone, so expect follow-ups on trade-offs, numbers and ho…
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Murugavel Ganesan
January 03, 2025
Top 50
Physical design interviews test whether you can take a synthesised netlist to a clean, sign-off ready layout: floorplanning, power planning, placement, clock tree synthesis, routing, timing closure and physical verification. The 50 questions below are the ones that come up most often, from basic concepts to tape-out, each with a short model answer. Use them to check your own answers, then expect the interviewer to push for numbers, trade-offs an…
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Murugavel Ganesan
January 03, 2025
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