Displaying posts in the categoryStatic Timing Analysis
Static Timing Analysis articles
Top 50
Physical design interviews test whether you can take a synthesised netlist to a clean, sign-off ready layout: floorplanning, power planning, placement, clock tree synthesis, routing, timing closure and physical verification. The 50 questions below are the ones that come up most often, from basic concepts to tape-out, each with a short model answer. Use them to check your own answers, then expect the interviewer to push for numbers, trade-offs an…
by
Murugavel Ganesan
January 03, 2025
Top 50
VLSI interviews test whether you understand the whole path from RTL to silicon: logic design, timing, power, physical design, signal integrity, test and manufacturing. The 50 questions below are the ones that come up most often for VLSI design roles, each with a short model answer you can build on. Interviewers rarely stop at the definition, so for each topic expect a follow-up on trade-offs, numbers or a problem you solved on a real project. …
by
Murugavel Ganesan
January 03, 2025
Synthesis
A multi-cycle path is a timing path that the design intends to take more than one clock cycle, so static timing analysis (STA) should check it against a later capture edge. A false path is a path that can exist structurally but is never required to carry a change that must be captured in a given time, so STA should not time it at all. Both are timing exceptions: constraints that override the default single-cycle check. Set correctly, they stop t…
by
Murugavel Ganesan
November 28, 2023
Tutorials
A multicycle path is a timing path between two registers on related clocks where the design intentionally gives the data more than one clock period to arrive. The logic is built so the destination only uses the value every N cycles, typically through a clock enable, so the default single-cycle check is too strict. You tell the timing tool about that intent with a multicycle path constraint, and you must adjust the hold check at the same time, or…
by
Murugavel Ganesan
November 21, 2023
Tutorials
An inverter outputs the logical complement of its input; a buffer outputs the same logic value, and in CMOS it is normally built as two inverters in series. For the same output drive, an inverter is smaller and faster because it has one stage instead of two, while a buffer keeps polarity, which makes it the easy drop-in choice for repeaters, fanout splitting and hold fixing. In timing closure both are used to repair long wires, high fanout and b…
by
Murugavel Ganesan
November 21, 2023
Tutorials
You decide on a clock network by starting from the chip's timing, power and variation budgets, then picking the cheapest distribution structure that meets them. A plain buffered clock tree, built by clock tree synthesis, suits most ASIC blocks. Balanced H-trees, fishbone (spine) structures and tree-driven meshes are used when skew, on-chip variation or very high frequency make a simple tree too risky, at the cost of more wire and power. Thi…
by
Murugavel Ganesan
September 01, 2023
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