Displaying posts in the categorySystemVerilog
SystemVerilog articles
Verification
IP and full chip verification interviews check whether you can prove a design correct before it becomes silicon. Expect questions on planning, SystemVerilog and UVM testbenches, constrained-random stimulus, coverage, assertions and formal, and on the system-level problems that only appear when every block is connected. The 50 questions below cover all of these, and each now has a short model answer. Verification is the backbone of chip desig…
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Murugavel Ganesan
January 03, 2025
Verification
Equivalence checking proves that two versions of the same design behave identically, for example RTL against the gate-level netlist produced by synthesis. Property checking proves that one design satisfies a set of properties written from the specification, such as "two grants are never active together". Both are formal methods that cover all input values without test vectors, but equivalence checking needs a trusted reference design, …
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Murugavel Ganesan
August 26, 2023
Verification
Formal verification is the use of mathematical analysis, rather than test vectors, to prove that a chip design meets its specification. A formal tool takes the RTL and a set of properties (assertions about how the design must behave) and either proves each property holds for every possible input sequence and reachable state, or returns a counterexample trace that shows exactly how it fails. In semiconductor engineering it is used to find corne…
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Murugavel Ganesan
August 26, 2023
Verification
This opening is in Bangalore, India and the company is looking forward to close it at the earliest Job Description: 1. About 5-7 years of experience in functional verification with at least 3-4 years in HVL's like E language/specman and System Verilog. 2. Good experience at both module and sub-system/SOC level verification 3. Good knowledge of Verilog/VHDL 4. Good knowledge of UVM/eRM methodology 5. Should have developed complete test ben…
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Murugavel Ganesan
March 20, 2012
Verification
Mentor Graphics provides the Methodology kit examples in open source form under the Apache-2.0 license. These kits are available for Questa versions 6.2 to 6.4
Verification
This matrix illustrates (SupportNet access needed) the version compatibility between Questa SV/AFV and different versions of OVM, Questa MVC Library, QVL, 0-In and Questa ADMS.
Verification
Case Study:SystemVerilog VMM vs. BSV for an Ethernet MAC test bench. High-level verification languages and environments such as e/Specman, Vera and now SystemVerilog, as used in VMM or OVM, may be the state-of-the-art for writing test bench IP, but they are not synthesizable for developing models, transactors and test benches to run in FPGAs for emulation and prototyping. So engineers wishing to move verification assets onto FPGAs have been des…
Verification
Hardware verification languages (HVLs) and verification IP (VIP) are the two ideas that moved chip verification from hand-written directed tests to reusable, randomised testbenches. An HVL such as SystemVerilog or e adds randomisation, constraints, coverage and object-oriented code to the testbench. A VIP is a ready-made, protocol-aware verification component, for example for PCIe or USB, built on a standard methodology so it plugs into any comp…
VHDL
VHDL is a strongly typed, verbose hardware description language with a rich type system, a well-defined standard and good support for large, structured designs. Verilog is smaller and quicker to write for simple circuits, and its successor SystemVerilog adds the verification features that dominate most ASIC flows today. SystemC and other C-based approaches trade hardware precision for familiar software syntax and faster system modelling. Which o…
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Murugavel Ganesan
July 30, 2007
