Displaying posts in the categoryLow Power Design
Low Power Design articles
SoC Design
In chip and system design, PPA (performance, power and area) are the three numbers every team argues about. You can usually improve any one of them, but almost never without paying for it in the other two. Image: SemiWiki The catch is that the best chip on paper is not always the best product in the market. From ADAS processors to AI accelerators, a PPA trade-off is a business decision as much as an engineering one. The wrong choice can hu…
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Murugavel Ganesan
July 08, 2025
Top10
The RTL coding mistakes that cost the most power and area are the ones that make logic toggle when it does no useful work, or that build more hardware than the function needs. Clocks that run when registers hold their value, glitchy deep logic, oversized buses, resets on every flop and accidental latches are the usual culprits. Synthesis tools recover some of this, but they cannot undo an architecture or coding style that asks for waste. Below a…
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Murugavel Ganesan
April 07, 2025
Top 50
VLSI interviews test whether you understand the whole path from RTL to silicon: logic design, timing, power, physical design, signal integrity, test and manufacturing. The 50 questions below are the ones that come up most often for VLSI design roles, each with a short model answer you can build on. Interviewers rarely stop at the definition, so for each topic expect a follow-up on trade-offs, numbers or a problem you solved on a real project. …
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Murugavel Ganesan
January 03, 2025
Tutorials
To benchmark an FPGA accelerator fairly, measure three things on the same realistic workload: performance (throughput, latency and speedup over a baseline), power and energy (measured at the board or wall, not only estimated), and accuracy (error against a trusted reference). Report them together, because an FPGA design can trade one against the others, for example by using lower-precision arithmetic to gain speed and save power at some cost i…
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Murugavel Ganesan
December 14, 2023
Low Power Design
Your task is to do power analysis for a circuit that sends out a one-clock-cycle pulse on the done signal once every 16 clock cycles(done is ’0’ for 15 clock cycles, then ’1’ for one cycle, then repeat with 15 cycles of ’0’ followed by a ’1’, etc). You have been asked to consider three different types of counters: 1. Binary counter, 2. Gray-code counter, and 3. One-hot counter. (The table below shows the values from 0 to 15 for the different en…
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Murugavel Ganesan
March 03, 2011
Physical Design
The objective here is to explore placement techniques which can lead to reduction in IR drop. One way to do this is to place high current cells towards the periphery in a peripheral i/o design. Simple way to implement this is to have a fixed dummy block at the center of the chip and attach fake nets from it to cell instances in a DEF file. A commercial placer can then be used to place this netlist. After placement, fake blocks and nets can be de…
Physical Design
Power gating adds enabling signals to a power supply network; dynamic power supply management adjusts supply voltage according to data path criticality. You are asked to take a testcase and upgrade its power supply network to dynamic power supply. How can you verify the power reduction of your technique?
Static Timing Analysis
This task usually starts with a placed and routed design, then generating a transistor level netlist for it and further optimizing it. Optimization can be for example adjusting transistor widths, or assigning different transistor threshold voltages in a dual threshold voltage design. This can be done algorithmically (e.g. TILOS) or in an ad-hoc fashion. See how much timing improvement you get vs. just gate-level optimization. Also notice any &qu…
SoC Design
This paper , using an example design, demonstrates how to meet challenging performance, latency and bandwidth goals by using the DesignWare Interconnect Fabric for the ARM AMBA 3 AXI while minimizing the total area, power consumption and number of top-level wires. The paper also studies the design requirements and examines the optimization features of the DesignWare Interconnect Fabric used to meet the stringent timing requirements. Detailed tec…
Mobile and Telecom
Displays have always been a major power consumer in mobile devices. In the past, one easy way to keep power demands in check was to limit the display performance in terms of luminance, color gamut, resolution and refresh rate. This way, users could get away without recharging their devices for several days. By contrast, today's power-hungry devices must be charged every day. Typical color displays require 400-500 mW, which is ~50% of the ave…
Power Electronics
Systems designers are having a difficult time developing power subsystems that supply all of their system's power needs due to varied and changing power requirements. A new type of power subsystem, the field-programmable power subsystem or FPPS, squarely addresses this issue by providing a flexible approach that costs no more than conventional switching power subsystems. This white paper discusses the advantages and benefits of field-progra…
Static Timing Analysis
No, latches are not bad in themselves. A latch is a perfectly valid storage element, and many high-performance and low-power designs use them deliberately for time borrowing and clock gating. What is bad is a latch nobody intended, or a latch whose enable is glitchy or poorly timed. Used on purpose, with a clean enable and proper timing constraints, a latch is a sound engineering choice. It is not completely correct to say that we have to avoi…
Processors
Cool Chips 2009 IEEE Symposium on Low-Power and High Speed Chips Yokohama, Japan April 15-17, 2009 COOL Chips is an International Symposium initiated in 1998 to present advancement of low-power and high-speed chips. The symposium covers leading-edge technologies in all areas of microprocessors and their applications. The COOL Chips XII is to be held in Yokohama on April 15-17, 2009, and is targeted at the architecture, design and implementation …
Verification
An in-depth technical webinar focusing on low power verification methodology. On Tuesday, March 31, 2009 5:00 pm, Pacific Daylight Time (GMT -07:00, San Francisco) Panelist(s) Info: Krishna Balachandran, Director of Low Power Verification Marketing, Srikanth Jadcherla, Group R&D Director, Janick Bergeron, Synopsys Fellow Duration: 1 hour Description: Power management and low power design bring a whole new assortment of bugs and failure me…
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Murugavel Ganesan
March 19, 2009
Power Electronics
EETimes has published an article on the Top 10 Power Management articles of 2008. {Follow Here}
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The Editor's Desk
January 22, 2009
Static Timing Analysis
These Hynix Semiconductor interview questions, first published here in December 2008, focus on backend and timing skills: power optimisation across the physical design flow, timing fixes before and after layout, process technology challenges, clock dividers, multicycle and false paths, hold violations, RTL coding for good backend results and timing diagrams. Hynix is now SK hynix, and the questions remain standard for memory and logic design rol…
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The Editor's Desk
December 13, 2008
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