Displaying posts in the categoryDFT and Test
DFT and Test articles
Process Technology
Building an automotive chip on a commercial wafer process and then qualifying it to AEC-Q100 is sometimes the only option, but on mature nodes it is usually a false saving. AEC-Q100 shows that sampled parts survived a set of stress tests; it does not make the silicon as robust as a process built for automotive. What you save on wafers you tend to spend again on screening, yield loss, test time and field reliability risk. In the semiconductor w…
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Murugavel Ganesan
December 12, 2025
DFT and Test
Hardware survives real-world failures when it is designed to recover from faults, built from parts rated for the actual environment and lifetime, stress-tested beyond functional checks, and instrumented so that field failures can be diagnosed. Consumer and automotive electronics apply these same four principles at very different strengths: a phone can lean on a reboot or a software patch, while a car's electronic control unit (ECU) must de…
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Murugavel Ganesan
May 06, 2025
Top 50
Design for Test (DFT) interviews test whether you understand how a chip is made testable after manufacture: scan insertion, fault models, ATPG, test compression, boundary scan, memory and logic BIST, and how coverage turns into shipped quality. The 50 questions below are the ones that come up most often, each with a short model answer you can build on. Interviewers rarely want definitions alone, so expect follow-ups on trade-offs, numbers and ho…
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Murugavel Ganesan
January 03, 2025
Tutorials
IJTAG (Internal JTAG) is the common name for IEEE 1687, a standard published in 2014 for accessing and operating the instruments embedded inside a chip, such as BIST engines, sensors, PLL and I/O controls and debug logic. It uses the existing JTAG (IEEE 1149.1) test access port as the way in, adds a reconfigurable on-chip scan network so that only the instruments you need are in the scan path, and defines two description languages: ICL for how t…
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Murugavel Ganesan
August 25, 2023
Tutorials
The stuck-at fault (SAF) model assumes that a single signal line in the circuit is permanently fixed at logic 0 or logic 1, and it is tested with one pattern applied at any speed. The transition-delay fault (TDF) model assumes that a line is too slow to rise or too slow to fall, and it is tested with a pair of patterns: the first sets the line to its starting value, the second launches the transition, and the result is captured one functional cl…
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Murugavel Ganesan
March 22, 2023
Verification
Design for Debug (DFD) means building features into a chip, and habits into the design flow, that make failures quick to find after silicon arrives. The ten strategies that do the most to manage debug complexity are: a modular architecture, standard interfaces, careful trace signal selection, abstraction during pre-silicon verification, design reuse, verification metrics to guide debug logic, detailed documentation, regular design reviews, DFT f…
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Murugavel Ganesan
March 19, 2023
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