An FPGA is a ready-made chip you program in the field, an ASIC is a chip designed from scratch for one job, and a structured ASIC sits between them: a pre-built array of logic that is customised with only a few metal or via masks. FPGAs win on flexibility and time to market, ASICs win on unit cost, speed and power at high volume, and structured ASICs offer a middle path with lower NRE than an ASIC and better unit cost and power than an FPGA. The right choice depends mostly on volume, schedule and how likely the design is to change.
Key takeaways
- FPGA: no mask cost, fastest to market, highest cost and power per unit.
- ASIC: highest NRE and longest schedule, lowest unit cost and best performance and power.
- Structured ASIC: fewer custom masks, so NRE and schedule are moderate, and unit cost and power are between the other two.
- Volume decides most cases. A simple break-even calculation shows where each option becomes cheapest.
- A common path is FPGA for prototyping, then a structured ASIC or full ASIC for production.
If you are looking for a high-performance, low-cost and low-power solution for your custom IC design, you might be wondering whether to choose an FPGA, an ASIC or a structured ASIC. This post explains what these terms mean, how they differ, and the advantages and disadvantages of each option.
What is an FPGA
FPGA stands for Field-Programmable Gate Array. It is a type of integrated circuit that can be reconfigured in the field by the user. An FPGA consists of an array of logic blocks that can perform different functions, such as arithmetic, memory or logic operations. These logic blocks are connected by a programmable interconnect network that allows the user to define the functionality of the FPGA. FPGAs are widely used for prototyping, testing and implementing complex digital systems.
Modern FPGAs also include hard blocks such as DSP slices, block RAM, high-speed transceivers, memory controllers and sometimes processor cores. The programmable routing that gives an FPGA its flexibility is also its main overhead: much of the silicon area and delay goes into switches and wires that a fixed design would not need.
What is an ASIC
ASIC stands for Application-Specific Integrated Circuit. It is a type of integrated circuit that is custom-designed for a specific application or function. An ASIC is optimised for performance, power and cost, but it requires a large upfront investment in design tools, verification and fabrication. ASICs are typically used for high-volume production of specialised devices, such as processors, sensors or communication chips.
In a standard-cell ASIC every layer of the chip is custom, so the design team needs a full mask set, which at advanced nodes is a large part of the NRE. A bug found after tape-out usually means a respin, adding months and new mask costs.
What is a structured ASIC
A structured ASIC is a type of integrated circuit that lies between FPGA and ASIC in terms of cost, performance and flexibility. A structured ASIC consists of a regular array of predefined logic cells that can be customised by one or more metal or via masks. A structured ASIC has lower NRE (non-recurring engineering) cost than an ASIC because it uses fewer custom masks and leverages existing fabrication processes. A structured ASIC also has higher performance and lower power consumption than an FPGA because it eliminates the overhead of programmable interconnects and logic blocks.
The base wafers, with transistors and lower metal layers already made, can be built in advance and stored. Only the top customisation layers are made for each customer, which shortens the schedule. eASIC was a well-known supplier of this approach, using a single via layer for customisation. Intel acquired eASIC in 2018 and later offered it as Intel eASIC devices, sometimes as a lower-cost, lower-power follow-on to an FPGA prototype. Altera's earlier HardCopy family followed a similar idea.
Comparison table
The following table summarises some of the key differences between FPGA, ASIC and structured ASIC. The ratings are relative, not absolute.
| Feature | FPGA | ASIC | Structured ASIC |
|---|---|---|---|
| Engineers needed | Low | Medium-High | Low |
| Tooling needs | Low | High | Medium |
| Engineering investment | Lowest | High | Low |
| Upfront cost | Low | High | Medium |
| Per-unit cost | High | Low | Medium |
| Performance | Low | High | Medium |
| Power consumption | High | Low | Medium |
| Flexibility | High | Low | Medium |
| Time to market | Short | Long | Medium |
| Design complexity | Low | High | Medium |
Note: the first version of this table listed ASIC power consumption as High. That contradicted the text above, since ASICs are optimised for power, and has been corrected to Low.
A worked break-even example
The prices below are illustrative, chosen to show the method. Real figures vary widely with node, die size and supplier.
| Option | NRE (illustrative) | Unit cost (illustrative) |
|---|---|---|
| FPGA | $0 | $150 |
| Structured ASIC | $1.5 million | $25 |
| ASIC | $15 million | $8 |
Total cost is NRE plus volume times unit cost. The break-even volume between two options is the difference in NRE divided by the difference in unit cost:
- FPGA versus structured ASIC: $1.5M / ($150 - $25) = 12,000 units.
- Structured ASIC versus ASIC: ($15M - $1.5M) / ($25 - $8), about 794,000 units.
- FPGA versus ASIC directly: $15M / ($150 - $8), about 106,000 units.
With these numbers, an FPGA is cheapest below about 12,000 units, a structured ASIC from there to about 800,000 units, and a full ASIC above that. Change the inputs and the boundaries move, but the shape of the answer stays the same. Remember to add schedule: if a full ASIC takes a year longer, the revenue lost from late entry can outweigh the unit savings.
How to choose
As you can see, there is no clear winner among these options. The best choice depends on your design requirements, budget and market conditions. However, some general guidelines are:
- Use an FPGA if you need fast prototyping, frequent changes or low-volume production.
- Use an ASIC if you need high performance, low power or high-volume production.
- Use a structured ASIC if you need a balance between cost, performance, power and flexibility.
Common mistakes
- Comparing only unit prices and ignoring NRE, schedule and respin risk.
- Assuming an FPGA design will move to an ASIC unchanged. Hard IP, clocking and memories usually need rework.
- Ignoring supply life: some structured ASIC and FPGA families have long-term supply commitments, others do not.
- Choosing an ASIC for a standard that is still changing, when a programmable part would avoid a respin.
FAQ
Is a structured ASIC the same as a gate array?
It is a close descendant. Classic gate arrays customised several metal layers over a sea of transistors; structured ASICs use larger pre-built cells and fewer custom layers.
Why is an FPGA slower than an ASIC?
Signals pass through programmable switches and longer routes, and logic is built from look-up tables rather than optimised gates, which adds delay and power.
When does an FPGA make sense in production?
For low volumes, for products that need field updates, and for markets where standards are still moving.
We hope this post has helped you understand what a structured ASIC or eASIC is, how it compares with a traditional ASIC, and how both compare with an FPGA. If you have any questions or comments, please feel free to contact us.
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