Chiplets are smaller dies, each built for one job (compute, I/O, memory, accelerators), that are assembled in one package and behave as a single system-on-chip. Instead of one very large monolithic die, a chiplet SoC splits the design, builds each part on the process node that suits it, tests each die before assembly, and joins them with dense die-to-die links on a silicon interposer, a bridge or a direct 3D bond. The result is better yield and reuse at the cost of packaging, interconnect and verification effort.
If you follow the latest trends in the semiconductor industry, you will have heard of chiplets. In this post we explain the concept, its benefits and challenges, how the pieces are actually assembled, and some current applications.
Key takeaways
- A chiplet is a die designed to be combined with other dies in one package, through a defined die-to-die interface.
- Smaller dies yield better, and each function can use the node that suits it (for example leading-edge logic with older-node I/O).
- Assembly options include organic substrates, 2.5D silicon interposers and bridges, and 3D stacking with hybrid bonding.
- UCIe (Universal Chiplet Interconnect Express), launched in 2022, is the main open die-to-die standard.
- The hard parts are interconnect power and bandwidth, thermal design, known good die testing, and multi-vendor trust.
What are chiplets?
Chiplets are small, modular dies that are combined to form a complete SoC. In a chiplet-based architecture several of them are connected inside one package to create a single, complex integrated circuit.
Unlike a traditional monolithic SoC, which puts every function on one piece of silicon, chiplets separate functions into specialised dies. A chiplet SoC could consist of a processor chiplet, a graphics chiplet, an AI accelerator chiplet and an I/O chiplet, with memory stacks alongside, each optimised for its task. By using chiplets, engineers can build complex products faster by assembling dies from their own teams or from third parties into a single package. These dies can hold I/O, memory, processor cores or any other function that can be packaged as a chiplet.
Where the idea came from
Putting several dies in one package is not new: multi-chip modules were used in mainframes decades ago. What changed in the last decade is the density of the links between dies and the push to make dies reusable across products. The US DARPA CHIPS programme (Common Heterogeneous Integration and IP Reuse Strategies), started in 2017, gave the modern idea a strong push by funding standard interfaces and reusable chiplets; Intel's Advanced Interface Bus (AIB) came out of that work.
The concept is also tied to Moore's law. In 1965 Gordon Moore, later a co-founder of Intel, observed that the number of components on a chip was doubling about every year; in 1975 he revised the rate to about every two years. As transistor scaling slowed and leading-edge wafers became far more expensive, building ever larger single dies became harder and costlier. Chiplets help extend the trend by letting a product grow beyond what one die can economically hold.
Why chiplets: the yield argument with numbers
A simple Poisson yield model shows why splitting a large die helps. Yield is roughly Y = exp(-A x D0), where A is die area and D0 is defect density. The numbers below are illustrative only.
| Design (illustrative) | Die area | Yield at D0 = 0.1 per cm2 |
|---|---|---|
| One monolithic die | 600 mm2 (6 cm2) | exp(-0.6), about 55% |
| One of four chiplets | 150 mm2 (1.5 cm2) | exp(-0.15), about 86% |
With the monolithic die, a defect anywhere scraps 600 mm2 of leading-edge silicon. With chiplets, a defect scraps only 150 mm2, and good chiplets from different wafers can be combined. The saving is partly offset by extra area for die-to-die interfaces, the cost of the package or interposer, and assembly yield, so the break-even point depends on die size, node cost and volume.
How chiplets assemble into an SoC
The package is where chiplets become one product. The main options, from cheapest and least dense to most dense, are:
| Approach | How dies connect | Examples |
|---|---|---|
| Organic substrate (2D MCM) | Bumps to a laminate substrate, wires routed in the substrate | AMD Ryzen and EPYC compute and I/O dies |
| Silicon interposer (2.5D) | Dies sit side by side on a passive silicon interposer with very fine wiring and TSVs | TSMC CoWoS for GPUs and AI accelerators with HBM; AMD Fiji (2015) |
| Embedded bridge (2.5D) | Small silicon bridges embedded in the substrate link only the die edges | Intel EMIB in Sapphire Rapids Xeon |
| Fan-out (RDL) | Redistribution layers built over moulded dies | TSMC InFO family |
| 3D stacking | Dies bonded face to face or face to back, by micro-bumps or hybrid bonding | Intel Foveros; AMD 3D V-Cache on TSMC SoIC |
Each chiplet also carries a die-to-die PHY and controller. On top of the physical link sits a protocol, often PCIe or CXL semantics carried over the die-to-die link, or a vendor's own fabric such as AMD Infinity Fabric.
What are the benefits of chiplets?
- Performance where it counts: specialised chiplets can be tuned for compute, graphics, AI or networking. The compute die can use the newest node while I/O, analog and SRAM-heavy parts that scale poorly stay on cheaper, mature nodes.
- Power management: separate dies can sit on separate power domains, so idle chiplets can be clocked down or powered off. Note the trade-off: moving data between dies costs more energy per bit than moving it on one die, so the partition must keep the busiest traffic on-die.
- Design flexibility: engineers can mix and match chiplets to build a product family, and can upgrade one die without redesigning the rest. Heterogeneous integration lets dies with different process technologies, materials or architectures share one package.
- Higher manufacturing yield: smaller dies yield better than one large die, as the example above shows. Chiplets can be tested as known good die (KGD) before assembly, which raises final package yield.
- Reusable IP: a proven chiplet, such as an I/O die, can be reused across many products, which cuts development cost and schedule.
What are the challenges of chiplets?
- Interconnects: the links between chiplets must be fast, reliable, scalable and power-efficient. Options include 2D and 2.5D packaging with flip-chip bumps and TSVs, 3D bonding, and, for longer reach, optical links such as co-packaged optics. Wireless RF links between dies have been researched but are not in mainstream products.
- Standards: without common standards, chiplets from different vendors cannot work together. Initiatives include UCIe (Universal Chiplet Interconnect Express), the Open Compute Project's Open Domain-Specific Architecture (ODSA) with its Bunch of Wires (BoW) interface, the Open Heterogeneous Integration Platform (OHIP), and Intel's Advanced Interface Bus (AIB). UCIe 1.0 was published in March 2022, and later versions (2.0 in August 2024) added support for 3D packaging and manageability.
- Thermal and mechanical: stacked and tightly packed dies concentrate heat, and different materials expand at different rates, which stresses bumps and bonds.
- Test: every die must be known good before assembly, and the assembled package needs access to each die for test and debug (IEEE 1838 defines a test access architecture for 3D stacks).
- Security and trust: chiplets from third-party vendors or untrusted supply chains raise risks of tampering, counterfeiting or malicious logic. Responses include authentication, encryption of die-to-die traffic, verification and isolation.
- Design and verification: partitioning, multi-die timing, power integrity and system-level verification now span several dies, often from different teams.
What are the applications of chiplets?
- PCs and servers: AMD has used chiplets in Ryzen and EPYC processors since Zen 2 (2019), combining several CPU compute dies (CCDs) with a separate I/O die that holds the memory controllers and I/O. The first-generation EPYC (2017) already used four dies in one package.
- Cloud computing: cloud providers customise silicon for their workloads. Amazon Web Services' Graviton3 is built from several dies, a compute die with separate memory and PCIe dies.
- Client devices: Apple's M1 (2020) is a monolithic SoC with its memory packages on the same substrate. Apple's chiplet step was the M1 Ultra (2022), which joins two M1 Max dies with its UltraFusion interconnect. Intel's Meteor Lake (2023) uses Foveros to stack compute, graphics, SoC and I/O tiles on a base die.
- High-performance computing and AI: Intel's 4th Gen Xeon Scalable (Sapphire Rapids, 2023) joins four compute tiles with EMIB bridges, and its Data Center GPU Max (Ponte Vecchio) combines dozens of tiles. AI accelerators routinely place large compute dies beside HBM stacks on silicon interposers.
- Automotive: carmakers and suppliers are studying chiplets to scale central compute across vehicle tiers while reusing qualified dies.
A related early example: AMD's Fiji GPU (Radeon R9 Fury, 2015) placed four high-bandwidth memory (HBM) stacks beside the GPU die on a silicon interposer. The HBM stacks themselves use through-silicon vias (TSVs). It was one of the first high-volume 2.5D products and showed what interposer-level integration could deliver in memory bandwidth.
How interviewers probe chiplets
- Why not one big die? Expect to explain the yield model, reticle size limits and node cost, and when monolithic still wins (small dies, very latency-sensitive traffic).
- How would you partition a design? Keep high-bandwidth, low-latency traffic on one die; put analog, I/O and SRAM-heavy blocks where they scale best.
- 2.5D versus 3D: know interposers, bridges and hybrid bonding, and the thermal trade-offs of stacking.
- What does UCIe define? A physical layer, a die-to-die adapter and protocol mapping (PCIe, CXL or streaming), for standard and advanced packages.
- Known good die: how you test a die before assembly and how you reach each die after assembly.
FAQ
Is a chiplet the same as an IP block?
No. An IP block is a design delivered to be placed on someone's die. A chiplet is a manufactured, tested die delivered to be placed in someone's package.
Do chiplets always reduce power?
Not automatically. Die-to-die links use more energy per bit than on-die wires, so power savings depend on good partitioning and on dense, efficient interfaces.
Is HBM a chiplet?
An HBM stack is a separate memory die stack placed in the package next to the logic die, so it is often counted as part of a chiplet system, although it predates the current use of the word.
What is UCIe?
Universal Chiplet Interconnect Express, an open standard for die-to-die links launched in 2022 by a group of chip, foundry and cloud companies, now run by the UCIe Consortium.
Videos
- The Rise of Chiplets in Advanced AI / ML / HPC SoCs, presented by Credo Semiconductor (Open Compute Project)
- Webinar: The Rise of the Chiplet (Achronix)
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