Gate-All-Around (GAA) Transistors: Intel 18A vs TSMC N2

Gate-all-around (GAA) transistors wrap the gate fully around stacked silicon channels (nanosheets or ribbons), giving better electrostatic control than FinFETs, whose gate covers only three sides of a fin. That control lets the transistor keep scaling with lower leakage and a tunable drive strength. Both Intel 18A (RibbonFET) and TSMC N2 are built on GAA, so the competition between them is decided less by the transistor type and more by yield, backside power delivery, design-kit maturity and customers.

As the industry pushes to smaller nodes, GAA marks the biggest change in transistor design since FinFETs arrived about a decade ago. This post explains how GAA works, why it matters, and how it shapes the race between Intel's 18A process and TSMC's 2 nm class N2 technology.

Courtesy: Semiconductor Engineering

Key takeaways

• GAA surrounds each channel with gate on all sides, which reduces short-channel effects and leakage compared with FinFETs.
• Channel width in a nanosheet device can be set by sheet width, not just by the number of fins, which gives designers finer drive-strength choices.
• Samsung was first to ship GAA (its 3 nm MBCFET, 2022). Intel 18A and TSMC N2 followed into volume production in late 2025.
• Intel 18A pairs RibbonFET with PowerVia backside power delivery; TSMC N2 uses front-side power, with backside power planned for its A16 node.
• Yield figures quoted in the press are unofficial; neither company publishes node yields.

Understanding GAA technology

A planar transistor has a gate on top of a flat channel. A FinFET raises the channel into a thin fin and wraps the gate over three sides. A GAA transistor goes one step further: the channel is split into several thin horizontal sheets stacked on top of each other, and the gate material fills the space around every sheet, so it touches all four sides.

Better gate control means the gate, rather than the drain, decides whether the channel conducts. That reduces drain-induced barrier lowering and subthreshold leakage, and allows a shorter gate length for the same off-state current. GAA devices can use nanowires (narrow, roughly round channels) or nanosheets (wider, flat channels). Production devices use nanosheets, typically three or four stacked, because wider sheets carry more current per footprint.

FinFET and GAA compared

Aspect	FinFET	GAA nanosheet
Gate coverage	Three sides of the fin	All sides of each sheet
Width control	Whole fins only (1, 2, 3 fins)	Sheet width can vary, plus number of sheets
Electrostatics at short gate lengths	Degrading below about 3 nm class	Better, allows further gate-length scaling
Process complexity	Mature	Higher: superlattice epitaxy, selective etch, inner spacers

Key advantages of GAA technology

Enhanced control and performance: the all-around gate gives tighter control of current flow, allowing higher drive current for a given footprint and leakage. This matters most for compute-heavy products such as AI accelerators and high-performance CPUs.

Reduced leakage currents: by surrounding the channel completely, GAA transistors cut the leakage that troubles FinFETs at the smallest gate lengths. Lower leakage means lower standby power and more room to lower the supply voltage.

Scalability: GAA allows scaling beyond what FinFETs can reach. As dimensions shrink, it becomes harder to keep fins tall, thin and uniform. Stacked sheets give more effective channel width per footprint, and designers can choose sheet widths to trade drive strength against area and power.

Comparing Intel 18A and TSMC N2

Both companies have adopted GAA, but they have made different choices around it.

Item	Intel 18A	TSMC N2
Transistor	RibbonFET (GAA nanosheet)	GAA nanosheet
Power delivery	PowerVia backside power	Front-side (backside Super Power Rail planned for A16)
Company-stated gains	Up to about 15% better performance per watt and about 30% higher density than Intel 3	About 10 to 15% more speed at the same power, or 25 to 30% less power at the same speed, versus N3E; over 15% higher density
Volume production	Late 2025 (Panther Lake client processors, Fab 52 in Arizona)	Fourth quarter of 2025 (Taiwan)
Main users	Intel's own products first; external foundry customers announced	Large external customer base, with Apple and AMD among the first announced or widely reported, and Nvidia reported as interested

Intel 18A

Intel brands its GAA transistor RibbonFET. The bigger difference is PowerVia, which moves the power-delivery network to the back of the wafer. Front-side metal is then free for signals, which eases routing congestion and reduces IR drop. Intel is the first to bring backside power and GAA together in volume. The cost is extra process steps, wafer thinning and bonding, and new thermal and debug considerations.

In late 2024 press reports claimed very low 18A yields (figures below 10% were quoted). Intel disputed those reports, and its leadership said defect density was on track. Intel then started volume production of Panther Lake on 18A in late 2025. Yields at a new node always start low and improve over many months, so a single reported number says little on its own.

TSMC N2

TSMC's N2 is its first GAA node. Press reports in late 2024 put early N2 test yields above 60%; TSMC does not publish yields but has said N2 is progressing well, and it started volume production in the fourth quarter of 2025. TSMC's strengths are manufacturing scale, a mature design ecosystem and a deep customer list. Apple has been widely reported as an early N2 customer, Nvidia has also been reported as an interested customer (not confirmed by either company), and AMD has announced an EPYC processor built on N2. TSMC plans N2P as a follow-on and A16, which adds backside power, after that.

What decides the race

• Yield and defect density at volume, which set cost per good die.
• Design enablement: PDKs, standard-cell and SRAM libraries, IP and EDA flows ready for customers.
• Backside power: Intel's early lead, against TSMC's front-side N2 and later A16.
• Customers and capacity: foundry success needs external customers committing high-volume products.

Challenges ahead

Manufacturing complexity: GAA fabrication grows alternating silicon and silicon-germanium layers by epitaxy, then removes the SiGe selectively to release the sheets, then forms inner spacers and wraps the gate stack around each sheet. Each step needs tight control, and new metrology is needed to inspect features buried between sheets. Both companies must master this to reach reliable mass production.

Design and testing difficulties: new device models, parasitic extraction, reliability rules and, for backside power, new floorplanning and debug methods are needed. Design teams must also re-characterise libraries and memories. As both companies chase higher performance and lower power, designs must stay manufacturable at scale without defects.

Cost: more process steps and EUV layers raise wafer cost, which pushes more products towards chiplets that use the leading node only where it pays off.

FAQ

Who shipped GAA first?

Samsung, with its 3 nm class MBCFET process, which entered production in 2022.

Is 18A really 1.8 nm?

No. Node names such as 18A, N2 or 3 nm are marketing labels. No single physical feature on the chip measures 1.8 or 2 nm.

Does N2 have backside power?

No. TSMC's N2 uses conventional front-side power delivery. Backside power arrives with its A16 node.

What comes after nanosheets?

The industry roadmap (for example imec's) points to forksheet devices and then complementary FET (CFET), which stacks n-type and p-type transistors on top of each other.