CoWoS vs EMIB: 2026 PPAC Decision Guide for Chiplet AI and HBM

Updated 2026

CoWoS or EMIB? If your product is bound by HBM bandwidth and needs many memory stacks next to one or two very large logic dies, TSMC's CoWoS family (today mostly CoWoS-L) is still the lowest-risk choice. If you are building a portfolio of chiplet products, need very large packages at a controlled cost, or want to mix dies from different nodes and sources, Intel's EMIB and the newer EMIB-T are increasingly strong options. The decision is made on power, performance, area and cost (PPAC) together with capacity, thermal and test, not on a single headline number.

CoWoS remains the reference for bandwidth density and HBM proximity, using an interposer (silicon in CoWoS-S, organic RDL with embedded silicon bridges in CoWoS-L). EMIB and EMIB-T scale in a modular way with small bridges placed only where dies meet, and they now approach finer pitches, better power delivery and the very large package sizes that HBM4 and UCIe designs call for.

Key takeaways

• CoWoS uses a full interposer under every die; EMIB embeds small silicon bridges in the package substrate only at die-to-die edges.
• For the highest aggregate HBM bandwidth with many stacks, CoWoS-L is the most proven path in volume AI accelerators.
• EMIB and EMIB-T reduce silicon area, isolate yield risk to small bridges and suit product families that reuse chiplets across SKUs.
• Die-to-die energy per bit depends as much on PHY, encoding and link design as on the packaging platform.
• In 2026, capacity (foundry, OSAT and substrate slots) and thermal solutions often set the schedule more than the packaging technology itself.

In this article

• Executive summary
• What is new in 2026
• Foundations: terms and metrics
• CoWoS deep dive
• EMIB and EMIB-T deep dive
• Performance and bandwidth
• Power, PI and energy per bit
• Area density and scaling
• Cost, yield and supply
• Thermal and reliability
• Ecosystem and roadmap
• Design levers for PPAC
• Decision framework
• Common mistakes
• FAQs (2026)
• Quick comparison table
• Launch checklist

Executive summary

The CoWoS family (S, R and L) leads for absolute HBM bandwidth density and uniform fabrics across the interposer. CoWoS-L's modular approach, with local silicon interconnect (LSI) bridges embedded in an RDL interposer, improves manufacturability and scale for two or more large logic dies with six or more HBM stacks. EMIB and EMIB-T emphasise modularity, cost, very large substrates and readiness for UCIe and HBM4, narrowing the gap in pitch and power delivery while keeping the flexibility to combine heterogeneous chiplets.

Bottom line: If the workload is hard HBM-bandwidth-bound and latency sensitive, CoWoS variants are the safest choice. If portfolio reuse, cost and rapid SKU spin-ups matter most, especially on very large substrates, EMIB and EMIB-T are increasingly compelling.

What is new in 2026

• HBM4 (JEDEC JESD270-4, published April 2025) doubles the interface to 2,048 bits per stack, and late HBM3E parts push pin speeds higher. Package signal integrity, power integrity and thermals now gate system performance as much as the compute dies.
• CoWoS-L scales the interposer concept with LSI bridges, enabling larger formats and better yield than a single monolithic silicon interposer while keeping very wide fabrics. TSMC has publicly described a path to interposers several times the reticle size in 2026 and 2027.
• EMIB-T, announced by Intel Foundry in 2025, adds through-silicon vias (TSVs) in the bridge for power and signal delivery, targets finer bump pitches, aligns with UCIe and HBM4, and is aimed at very large organic (and later glass) substrates.
• Capacity planning is strategic. Aligning foundry and OSAT slots, substrate lead times and thermal solution supply is critical to a predictable product introduction.

Foundations: terms and metrics

Clear terms prevent people talking past each other in reviews.

• PPAC: power, performance, area and cost. Teams often extend it to PPAC-T for thermal or PPAC-R for reliability.
• HBM3E and HBM4: stacked DRAM placed on the package beside the logic. Bandwidth density and proximity to the logic dominate system performance for AI and HPC.
• Interposer: a passive layer between the dies and the package substrate that carries very fine wiring between dies. It can be silicon (with TSVs) or organic redistribution layers (RDL).
• Bridge: a small piece of silicon with fine wiring, embedded in the substrate or interposer, that connects only the edges of neighbouring dies.
• UCIe: the Universal Chiplet Interconnect Express die-to-die standard. The advanced-package variant assumes bump pitches of roughly 25 to 55 µm; the standard-package variant uses about 100 to 130 µm. PHY feasibility depends on bump pitch, SI/PI and package topology.
• NoP: network-on-package. Link width, encoding, equalisation and topology (mesh, star or ring) set energy per bit and latency.
• Reticle limit: the largest area a lithography scanner exposes in one shot, about 26 mm by 33 mm (858 mm²). Larger interposers are built by stitching exposures or by using bridges.

CoWoS deep dive

Architecture

CoWoS (chip on wafer on substrate) places logic and HBM on an interposer, giving very wide, short routes with tight micro-bump pitches for extreme bandwidth and low latency. There are three main flavours:

• CoWoS-S: a large monolithic silicon interposer with TSVs. It offers the finest wiring but its size and yield are limited by stitching a single large piece of silicon.
• CoWoS-R: an organic RDL interposer with no silicon interposer, lower cost and more mechanical compliance, but coarser wiring.
• CoWoS-L: an RDL interposer with small LSI bridges embedded where dies need fine-pitch links, plus optional integrated passive devices (IPDs) for decoupling. It composes a large interposer from smaller silicon pieces to scale size, yield and cost.

The cross-section above shows the CoWoS-L idea: the SoC and HBM stacks sit on a moulded RDL interposer, LSI bridges carry the dense SoC-to-HBM wiring, an IPD adds local decoupling, and through-insulator vias (TIVs) take power and signals down to the substrate. NVIDIA's Blackwell B200, with two reticle-sized dies and eight HBM3E stacks, is built on CoWoS-L.

Strengths

• Highest aggregate HBM bandwidth density with uniform wiring across the whole interposer.
• Predictable SI/PI with an engineered interposer power delivery network (PDN) and decoupling options such as deep trench capacitors and IPDs.
• A straightforward path for UCIe-class PHYs on interposer metal.
• Mature enablement: HBM vendors, IP providers and EDA flows have years of CoWoS production behind them.

Trade-offs

• Interposer silicon and TSV processes raise cost and yield sensitivity, most of all in CoWoS-S.
• Heat concentrates under dense logic and multiple HBM stacks, which calls for advanced cooling.
• Interposer stitching limits are reduced but not removed; CoWoS-L helps.
• Capacity has been tight since 2023, so slots must be booked early.

EMIB and EMIB-T deep dive

Architecture

EMIB (embedded multi-die interconnect bridge) embeds small silicon bridges in an organic substrate to connect neighbouring dies at high density without a full interposer. Signals that do not need fine pitch, and all power, go through the normal substrate. Intel has shipped EMIB in volume since 2017, first in Stratix 10 FPGAs and later in Xeon processors such as Sapphire Rapids and in data centre GPUs combined with Foveros 3D stacking. EMIB-T adds TSVs through the bridge, so power and signals can pass vertically through it, supports larger package formats and targets finer pitches suited to UCIe and HBM4.

The Stratix 10 example above shows the principle: the FPGA and transceiver dies sit directly on the substrate, and an EMIB bridge under their adjacent edges carries the fine-pitch links, while package traces handle everything else.

Strengths

• Modular, targeted high-speed links reduce total silicon area and cost.
• Scales to very large packages by distributing many bridges.
• Heterogeneous chiplet integration and reuse across SKUs are straightforward.
• Bridges are small, so a defect scraps a small piece of silicon rather than a whole interposer.

Trade-offs

• Less uniform than a full interposer fabric; the design must plan local high-bandwidth corridors.
• Bridge placement accuracy and substrate complexity demand tight co-design.
• Aggregate bandwidth can lag interposer-class fabrics without careful floorplanning.
• Fewer third-party designs have gone through the flow so far, so the external ecosystem is younger than CoWoS.

Performance and bandwidth

For training-class AI and large HPC, system performance is often bound by memory bandwidth rather than compute. CoWoS's wide interposer routes minimise latency and maximise concurrency to many HBM stacks, keeping headroom for scaling. EMIB delivers high bandwidth per bridge and can approach similar aggregate figures by adding bridges and optimising die adjacency; EMIB-T's power delivery improvements further raise sustainable throughput.

Worked example: HBM bandwidth per package

Peak HBM bandwidth per stack is interface width times pin rate:

• HBM3E at 8 Gb/s per pin: 1,024 bits × 8 Gb/s = 8,192 Gb/s, or about 1.02 TB/s per stack. Eight stacks give about 8.2 TB/s, which matches the roughly 8 TB/s quoted for B200-class parts.
• HBM4 at 8 Gb/s per pin: 2,048 bits × 8 Gb/s = 16,384 Gb/s, or about 2.05 TB/s per stack. Eight stacks give about 16.4 TB/s.

Each HBM4 stack needs twice the signal count at the base die edge. Whatever platform you choose has to route about 2,000 data signals, plus command, clock and power, per stack within a few millimetres. That is why HBM adjacency and bump pitch dominate the floorplan.

Heuristic: if model performance scales nearly linearly with memory bandwidth in profiling, prefer interposer-class fabrics. If it saturates earlier or tolerates topology, EMIB may be enough.

Power, PI and energy per bit

Short interposer links allow low I/O swing and low energy per bit, while an interposer PDN (RDL, deep trench decoupling) stabilises the supply at high toggle rates. EMIB's short bridges are also efficient, and EMIB-T's TSV power paths reduce droop across very large substrates. In both cases, adaptive equalisation and encoding on the NoP strongly affect joules per bit, often more than the packaging platform itself.

• Interposer: lower baseline energy per bit and excellent PI; may need aggressive thermal design to sustain clocks under hotspots.
• EMIB and EMIB-T: competitive energy per bit with careful link design; distributed heat sources can be easier to cool at package scale.

Worked example: what energy per bit costs (illustrative)

Suppose two compute dies exchange 10 TB/s, which is 80 Tb/s. Die-to-die link power is bandwidth times energy per bit:

Energy per bit (illustrative)	Link power at 80 Tb/s
0.3 pJ/bit	24 W
0.5 pJ/bit	40 W
1.0 pJ/bit	80 W

A difference of a few tenths of a picojoule per bit is tens of watts in a package that may already be over 1 kW. That power also lands in the hottest part of the package, at the die edges. This is why PHY choice and link utilisation deserve as much attention as the platform.

Area density and scaling

CoWoS achieves tight pitch and dense routing across large, stitched interposers; CoWoS-L extends scale with modular LSI bridges. EMIB scales by adding bridges where needed, with organic (and in future glass) substrates enabling very large body sizes. Practical limits come from assembly yield, warpage and co-planarity rather than routing alone.

A useful way to compare is shoreline bandwidth: how many terabytes per second you can move across each millimetre of die edge. Fine-pitch platforms (silicon interposer, LSI or EMIB bridges at 25 to 55 µm) give far more bandwidth per millimetre than standard organic packaging at 100 µm or more. As an illustrative example, if a link delivers 1 TB/s per millimetre of edge and two dies need 4 TB/s between them, you must reserve about 4 mm of edge on each die for that link, before counting HBM interfaces.

Cost, yield and supply

CoWoS-S's interposer drives silicon area cost and ties yield to a large die-like structure; CoWoS-L reduces some of this risk. EMIB reduces silicon exposure and confines yield risk to bridges and die sites, often improving economics across a product family. In 2026, capacity allocation (foundry, OSAT and substrate) is often the real schedule bottleneck, so secure slots early.

Worked example: compounded assembly yield (illustrative)

Multi-die packages multiply risk. If each die attach succeeds 99.5% of the time and a package has 2 logic dies, 8 HBM stacks and 2 I/O dies (12 attaches), assembly yield is 0.995¹², about 94.2%. If the package carries USD 5,000 of known-good silicon, losing 5.8% of packages costs about USD 290 per good unit before any interposer or bridge loss is counted. Better known-good-die (KGD) testing, rework where possible and fewer, larger silicon parts in the passive layer all move this number.

Programme risk: packaging capacity and substrate lead times can dominate time to market. Build contingencies into your launch window and evaluate multi-sourcing where feasible.

Thermal and reliability

CoWoS concentrates heat under the logic and adjacent HBM, demanding premium thermal interface materials (TIMs), lids, vapour chambers and sometimes liquid cold plates. EMIB avoids full-interposer warpage risks and benefits from distributed heat paths in very large packages. For both, thermomechanical simulation must include temperature cycling, coefficient of thermal expansion (CTE) mismatch, underfill choice and lid attach process windows. HBM stacks have tighter temperature limits than logic, so the hottest logic should not sit directly against the memory if the floorplan allows otherwise.

Ecosystem and roadmap

CoWoS is deeply integrated with HBM, IP and EDA package co-design flows, and the shift to CoWoS-L increases manufacturable size without giving up interposer-class fabrics. EMIB remains central to Intel's bridge-based multi-die strategy and is often combined with Foveros 3D stacking. EMIB-T aligns with UCIe and HBM4 and targets finer pitches and very large packages. Intel Foundry offers EMIB to external customers, which makes it a real second source for advanced packaging rather than an internal-only technology.

Design levers for PPAC

1) Partitioning and placement

• Granularity: fewer, larger chiplets simplify the NoP but may worsen yield; more, smaller chiplets improve binning but increase NoP complexity.
• HBM adjacency: place the HBM-bound engines closest to the memory; interleave cache slices to avoid hotspot corridors.
• Floorplanning: align bridge or interposer corridors with expected traffic; reserve escape channels for late PHY changes.

2) Network-on-package (NoP)

• Topology: mesh for uniformity, star for low latency to a hub, ring for area efficiency; consider hybrid topologies per quadrant.
• PHY: choose encoding, equalisation and clocking to minimise energy per bit at the target bit error rate for your chosen pitch.
• QoS: provision arbitration and virtual channel classes to avoid priority inversion under bursty AI training traffic.

3) PDN and decoupling

• Layering: co-optimise interposer or bridge PDN layers with package planes; avoid resonance bands near major clock harmonics.
• Decap: place deep trench or MIM decoupling close to aggressors; validate with transient current profiles, not just AC sweeps.

4) Thermal architecture

• Materials: high-performance TIMs, vapour chambers and flatness control are basic requirements at HBM4 power densities.
• Z-stack: consider heat spreaders aligned to the main corridors; separate HBM thermals from logic peaks where possible.

5) Test, yield and rework

• KGD: tighten known-good-die testing for bridges and PHYs; add boundary loopbacks per corridor.
• Rework: EMIB's modularity can simplify site-level rework; CoWoS needs robust up-front screening to reduce scrap.

Decision framework

Use this quick rubric to converge on the right platform:

If your situation is...	Favour
Workload is HBM-bound and latency sensitive across many channels	CoWoS or CoWoS-L
Portfolio breadth and SKU reuse are key, with rapid spins on a common substrate	EMIB or EMIB-T
Package must exceed traditional interposer reticle limits	CoWoS-L or EMIB-T
Strict cost targets and heterogeneous dies across nodes	EMIB or EMIB-T
Thermal solution budget is limited but area is plentiful	EMIB with distributed bridges
Earliest market window with a known HBM and IP flow	CoWoS with mature enablement

Common mistakes

• Comparing peak numbers only. Sustained bandwidth under thermal and PDN limits is what the workload sees.
• Treating CoWoS as one technology. CoWoS-S, CoWoS-R and CoWoS-L differ in interposer material, pitch, size and cost.
• Choosing the platform before the partition. Traffic between dies should drive the package, not the other way round.
• Ignoring assembly yield. With a dozen dies, small per-attach losses compound quickly.
• Booking capacity late. A design that is ready but has no packaging slot is not a product.

FAQs (2026)

Can EMIB match CoWoS aggregate bandwidth for AI training?

EMIB can approach CoWoS by adding bridges and optimising adjacency, and EMIB-T's power delivery advances help. CoWoS interposers still provide the most straightforward path to the absolute highest aggregate bandwidth with many HBM stacks.

Is UCIe better on one platform?

UCIe can run on both. CoWoS interposer wiring and EMIB-T's fine-pitch bridges are each viable. Feasibility depends on PHY pitch, loss budget, clocking and PDN noise more than on the platform's name.

What about glass substrates?

Glass improves dimensional stability and routing density at large formats, which benefits bridge-based packaging such as EMIB. TSMC is also exploring panel-level and glass options to extend size and reduce cost. Volume use of glass cores is expected later in the decade.

Can CoWoS and EMIB be combined?

Yes, as design approaches. Hybrids use local interposer-like regions or 3D stacking with bridge-connected chiplets elsewhere, trading uniform fabrics for modular reuse and cost control. CoWoS-L itself is a bridge-in-interposer hybrid.

How do I de-risk capacity?

Lock substrate and assembly slots early, align with foundry and OSAT quarterly ramps, and keep a dual-path package option if the bill of materials and schedule allow.

Quick comparison table

Dimension	CoWoS (S, R, L)	EMIB and EMIB-T
Core concept	Interposer under all dies (silicon in S, RDL in R, RDL with LSI bridges in L) for logic and HBM proximity and very wide routing	Local silicon bridges in an organic substrate; TSV-assisted power delivery in EMIB-T
Peak bandwidth density	Highest; multiple HBM stacks with uniform low-latency fabrics	High per bridge; aggregate improves with more bridges and optimised adjacency
Energy per bit and PI	Low energy per bit; strong PDN; thermal density can limit sustained clocks	Efficient short bridges; EMIB-T improves droop across large substrates
Scale limits	Interposer size and stitching; CoWoS-L eases manufacturability	Very large packages through more bridges; glass substrates will help
Cost and yield	Higher because of interposer silicon and TSVs (most in CoWoS-S); yield tied to large area	Less silicon area; modular risk isolation; favours portfolio reuse
Thermal and reliability	Hotspots and CTE mismatch need premium materials and cooling	Less warpage risk, distributed heat paths, standard assembly flows
Roadmap (2026)	CoWoS-L extends size and yield; strong HBM and IP enablement	EMIB-T aligns with HBM4 and UCIe; finer pitch and very large formats

Launch checklist

• Profile the workload: quantify bandwidth sensitivity versus compute.
• Lock the HBM generation and pin map; verify PHY pitch feasibility across corners.
• Co-design the NoP early with package corridors and decoupling zones.
• Thermal plan: TIM, lid, vapour chamber or liquid cooling; validate with transient hotspots.
• PDN: avoid resonance near core clock harmonics; verify droop under bursts.
• DFT and DFM: loopbacks on bridges, BIST on UCIe links, KGD rigour.
• Supply: secure substrate and assembly slots and contingency capacity.
• Cost: model yield learning curves; keep a fallback package path if possible.