The Art of Analog Layout by Alan Hastings (Prentice Hall, Pearson Education) is a practical textbook on laying out analog integrated circuits: device physics, process failure modes, parasitics and, above all, how to match devices. It is written for layout designers and keeps the mathematics to basic algebra. This page keeps the original book notes and adds a summary of the core analog layout ideas the book is known for.
Key takeaways
- The book covers three process families: standard bipolar, polysilicon-gate CMOS and analog BiCMOS.
- Its central theme is that layout geometry changes device behaviour, so matching, parasitics and reliability must be designed in, not checked afterwards.
- Core matching techniques include identical unit devices, common-centroid and interdigitated arrangements, dummy devices and keeping matched devices close together and in the same orientation.
- It is a commercial book. Buy or borrow it through a bookseller, publisher or library.
The Art of Analog Layout: book details (original post)
The Art of Analog Layout
by Alan Hastings (Author), Roy Alan Hastings (Author)
Book info
(Pearson Education) Provides layout designers with broad coverage of the issues involved in successfully laying out analog integrated circuits. Keeps mathematics to a minimum, provides a carrier-based model for understanding device operation, and offers many exercises that can be done with paper and pencil instead of software. DLC: Integrated circuits--Design and construction.
From the back cover
Based on the author's extensive experience as a circuit designer and a layout designer, The Art of Analog Layout takes a practical and authoritative perspective, providing the reader with broad coverage of the issues involved in successfully laying out analog integrated circuits. Topics range from the mechanics of layout to essential information about many related areas, such as device physics, processing failure modes and effects, device operation, parasitics, and matching. The emphasis throughout is on practical knowledge.
- Written for layout designers, the mathematics is kept to a minimum, requiring only a familiarity with basic algebra and elementary electronics.
- Provides a carrier-based model for understanding device operation.
- Focuses on three processes: standard bipolar, polysilicon-gate CMOS, and analog BICMOS, enabling the reader to comprehend most new processes.
- Discusses the ways in which variations in layout geometries affect the performance of devices fabricated in silicon.
- Many exercises can be completed using pencil and paper for those who do not have access to layout editing software.
Note (added 1 November 2026): the author links above still lead to an Amazon search page. The Art of Analog Layout is a copyrighted commercial book; please obtain it from the publisher, a bookseller or a library. "Alan Hastings" and "Roy Alan Hastings" appear to be two forms of the same author's name in the retailer's listing.
Why analog layout is different from digital layout
In digital design, a gate either meets timing or it does not, and place-and-route tools handle most of the layout. In analog design, the circuit's accuracy often depends on two devices being as close to identical as possible: the two transistors of a differential pair, the transistors of a current mirror, or the resistors and capacitors of a ratio. Small differences in size, position, orientation, temperature or stress turn into offset voltage, gain error and distortion. That is why analog blocks are still largely laid out by hand, and why a book focused on layout rather than circuit theory is so useful.
Core analog layout techniques
Matching
Mismatch has two parts. Random mismatch comes from local variation, such as dopant fluctuations and edge roughness, and falls as device area grows. A widely used rule (Pelgrom's law) says the standard deviation of the mismatch is roughly inversely proportional to the square root of the device area. Systematic mismatch comes from gradients across the die (oxide thickness, temperature, stress) and from layout asymmetry; area does not help, but layout does.
| Technique | What it fixes |
|---|---|
| Identical unit devices (same size, shape and orientation) | Ratio errors from edge effects; build a 4:1 ratio from five identical units, four plus one, rather than one large and one small device |
| Common-centroid arrangement (for example ABBA or a cross-coupled quad) | Linear gradients cancel because both devices share the same centre |
| Interdigitation (ABABAB) | Spreads both devices over the same area to reduce gradient effects |
| Dummy devices at the ends of an array | Makes the outermost units see the same surroundings as the inner ones (etch and lithography effects) |
| Close placement, same orientation, away from hot or stressed areas | Thermal gradients, package stress and orientation-dependent effects |
| Symmetric routing | Unequal wire resistance and parasitic capacitance between matched branches |
Worked example: common-centroid pair
Suppose a differential pair is split into two units each, and a linear gradient adds +1, +2, +3 and +4 units of error at four positions in a row. A side-by-side layout AABB gives A = 1 + 2 = 3 and B = 3 + 4 = 7, a difference of 4. A common-centroid layout ABBA gives A = 1 + 4 = 5 and B = 2 + 3 = 5, a difference of 0. The gradient cancels because both devices have their centre in the same place. A two-dimensional cross-coupled quad does the same for gradients in both directions.
Parasitics
Every wire has resistance and capacitance, and every junction has capacitance to the substrate. Analog layout keeps high-impedance and sensitive nodes short, avoids routing noisy digital lines over or next to them, and uses shields where needed. Current-carrying lines are sized for both voltage drop and electromigration.
Substrate noise and latch-up
Guard rings (rings of substrate or well contacts around a device) collect injected carriers and lower the substrate resistance, which reduces noise coupling between blocks and the risk of latch-up in CMOS. Separating analog and digital supplies and grounds serves the same goal.
Reliability and process effects
The book also covers failure mechanisms that layout can cause or prevent, such as electromigration, antenna effects during processing, hot-carrier effects and electrostatic discharge (ESD) protection. Modern foundries capture many of these rules in the process design kit; see our post on what a PDK is and why it matters.
Who should read it
- Analog and mixed-signal layout engineers, from new graduates to experienced designers moving to a new process.
- Analog circuit designers who want to understand what the layout team needs from them.
- Physical design engineers who work next to analog blocks. Our top 50 physical design interview questions covers the digital side of the same job family.
For why analog circuits still matter in a digital world, see top 10 advantages of analog circuits over digital circuits. The Semiconductor Hub glossary has short entries on common centroid and PDK.
Frequently asked questions
Who wrote The Art of Analog Layout?
Alan Hastings (also listed as Roy Alan Hastings). It is published by Prentice Hall, part of Pearson Education.
Is there a second edition?
Yes. A second edition followed the first; check the publisher or a bookseller for the current edition and ISBN.
Is The Art of Analog Layout good for beginners?
Yes. It assumes only basic algebra and elementary electronics, explains device physics with a carrier-based model, and includes pencil-and-paper exercises.
What is common-centroid layout?
A way of arranging the unit parts of two matched devices so that both share the same geometric centre. Linear process gradients then affect both devices equally and cancel.
Is The Art of Analog Layout available as a free e-book?
It is a commercial, copyrighted book. Buy it from the publisher or a bookseller, or borrow it from a library.
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