Displaying posts in the categoryTop 50
Top 50 articles
Top 50
The hardest part of automotive edge AI is not the chip itself but everything around it: power and heat in a sealed enclosure, safety certification of models that do not behave deterministically, security of over-the-air updates, and the cost of putting data-centre class compute into a mass-market car. Implementing edge AI in a vehicle is not just about fitting a faster processor; it means rebuilding the vehicle architecture so the car acts as a …
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Murugavel Ganesan
February 02, 2026
Verification
IP and full chip verification interviews check whether you can prove a design correct before it becomes silicon. Expect questions on planning, SystemVerilog and UVM testbenches, constrained-random stimulus, coverage, assertions and formal, and on the system-level problems that only appear when every block is connected. The 50 questions below cover all of these, and each now has a short model answer. Verification is the backbone of chip desig…
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Murugavel Ganesan
January 03, 2025
Top 50
Design for Test (DFT) interviews test whether you understand how a chip is made testable after manufacture: scan insertion, fault models, ATPG, test compression, boundary scan, memory and logic BIST, and how coverage turns into shipped quality. The 50 questions below are the ones that come up most often, each with a short model answer you can build on. Interviewers rarely want definitions alone, so expect follow-ups on trade-offs, numbers and ho…
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Murugavel Ganesan
January 03, 2025
Verilog
RTL design and micro architecture interviews test three things: whether you can describe hardware correctly in Verilog or SystemVerilog, whether you understand timing, clocking and reset well enough to build something that works on silicon, and whether you can reason about trade-offs in performance, power and area. The 50 questions below cover all three, from counters and FIFOs to pipelines, caches and clock domain crossing, and each one now com…
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Murugavel Ganesan
January 03, 2025
Top 50
Physical design interviews test whether you can take a synthesised netlist to a clean, sign-off ready layout: floorplanning, power planning, placement, clock tree synthesis, routing, timing closure and physical verification. The 50 questions below are the ones that come up most often, from basic concepts to tape-out, each with a short model answer. Use them to check your own answers, then expect the interviewer to push for numbers, trade-offs an…
by
Murugavel Ganesan
January 03, 2025
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