Displaying posts in the categoryDesign for Debug
Design for Debug articles
DFT and Test
Hardware survives real-world failures when it is designed to recover from faults, built from parts rated for the actual environment and lifetime, stress-tested beyond functional checks, and instrumented so that field failures can be diagnosed. Consumer and automotive electronics apply these same four principles at very different strengths: a phone can lean on a reboot or a software patch, while a car's electronic control unit (ECU) must de…
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Murugavel Ganesan
May 06, 2025
Tutorials
IJTAG (Internal JTAG) is the common name for IEEE 1687, a standard published in 2014 for accessing and operating the instruments embedded inside a chip, such as BIST engines, sensors, PLL and I/O controls and debug logic. It uses the existing JTAG (IEEE 1149.1) test access port as the way in, adds a reconfigurable on-chip scan network so that only the instruments you need are in the scan path, and defines two description languages: ICL for how t…
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Murugavel Ganesan
August 25, 2023
Verification
Design for Debug (DFD) means building features into a chip, and habits into the design flow, that make failures quick to find after silicon arrives. The ten strategies that do the most to manage debug complexity are: a modular architecture, standard interfaces, careful trace signal selection, abstraction during pre-silicon verification, design reuse, verification metrics to guide debug logic, detailed documentation, regular design reviews, DFT f…
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Murugavel Ganesan
March 19, 2023
SoC Design
Silicon debug is the work of finding out why a manufactured chip does not behave as intended, and tracing that failure to its root cause in the design, the manufacturing process or the test setup. It starts when first silicon comes back from the fab and continues through validation and early production. Because the inside of a chip is almost invisible, silicon debug depends on features designed into the chip in advance, on lab equipment, and on …
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Murugavel Ganesan
March 06, 2023
EDA Tools
nECO is an integrated graphical netlist modification tool for the Verdi and Debussy debug systems. The Novas debug systems accelerate users' understanding of complex designs to improve design, verification, and debug productivity. nECO adds the ability to isolate logic that needs to be changed in a flattened schematic, make the necessary changes, and write the modified design to a new netlist file.
RTL Design
The Identify RTL Debugger lets FPGA designers and ASIC prototyping designers to functionally debug their hardware directly in their RTL source code. This allows functional verification with RTL designs 10,000 times faster than RTL simulators, and enables the use of in-system stimulus for applications like networking, audio and video, and HW/SW designs. Identify software allows designers to directly select signals and conditions in their RTL sour…
DFT and Test
This paper provides a summary of the features and benefits from the new IEEE-1149.7 specification commonly referred to as compact JTAG (cJTAG) which builds on existing IEEE-1149.1 boundary-scan architecture.
Verification
"Debugging" is the most valuable engineering skills, not taught in any formal setting, and often learned the hard way, by trial, error, experience, and long days and nights. These excerpted chapters, part1 , part2 , part3 from a book, Debugging: The 9 Indispensable Rules for Finding Even the Most Elusive Software and Hardware Problems , published by AMACOM Books is informative and a logical introduction to the skill and art of begging…
