RTL Synthesis and Backend Interview Questions with Answers

These nine RTL synthesis and backend interview questions cover the physical design topics interviewers return to most: parallelising the flow, reading timing reports, fixing violations, Elmore delay, wire sizing, zero-skew clock trees, in-place optimisation, ordering a clock and place-and-route flow, and design file sizes. Each question has the short answer an interviewer expects, followed by a fuller explanation. Several earlier explanations on this page contained errors; they have been corrected and the corrections are listed at the end.

Key takeaways

• Parallel computing in the flow always means three things: partition, distribute, then integrate with consistent boundaries.
• Setup is fixed by making the data path faster or the clock slower; hold is fixed by adding delay. Slowing the clock never fixes hold.
• Elmore delay of an RC tree is computed in linear time with two passes: downstream capacitance bottom-up, then delays top-down.
• For a uniform wire the width cancels out of the wire's own RC delay; width helps only with driver and load effects, or when segments are sized differently (tapering).
• LEF describes the technology and library, so it hardly changes with gate count; routed DEF grows roughly in proportion to the design.

Q1: How would you speed up an ASIC design project by parallel computing?

Which design stages can be distributed for parallel computing, which cannot, and what procedures are needed for maintaining parallel computing?

Mentioning the following important steps in parallel computing is essential:

1. Partitioning the design
2. Distributing partitioned tasks among multiple CPUs
3. Integrating the results

Backend ASIC design involves several stages, including floorplanning, placement, clock tree synthesis, routing and physical verification, and each benefits from parallel computing to a different extent.

• Floorplanning decides where major blocks go and sets up the chip-level power and signal distribution. It is a global decision, so it is hard to split, although once the top-level partitions are fixed, each block can be floorplanned independently.
• Placement places cells to optimise timing, power and area. In a hierarchical design each block can be placed independently. A flat global placement is one large optimisation problem, so it is multithreaded inside the tool rather than split into separate jobs.
• Clock tree synthesis builds the clock distribution network. Separate clock domains, or the lower levels of a tree under a fixed top-level structure, can be built in parallel.
• Routing connects the cells and nets. Detailed routing splits naturally into regions (switch boxes or tiles) worked on in parallel; global routing must see the whole chip's congestion.
• Physical verification (DRC, LVS) checks the layout against the design rules. It partitions very well by area or by rule, which is why sign-off DRC routinely runs on many CPUs.

What stages: the following answers are acceptable. Others may be accepted with a reasonable explanation of why you can or cannot use parallel computing in a particular stage.

Can use parallel computing	Cannot (or only with difficulty)
Synthesis after partitioning	Synthesis before partitioning
Placement (hierarchical design)	Floorplanning
Detailed routing	Flat placement
DRC	Global routing
Functional verification
Timing analysis (partition the timing graph)

Constraints: mention that care must be taken to make sure partition boundaries are consistent when the results are integrated back together: pin locations, timing budgets for paths that cross partitions, and power grid alignment. Modern tools multithread even the "cannot" stages internally, so a strong answer separates distributing independent jobs from multithreading one job.

Q2: What kinds of timing violations are in a typical timing analysis report?

The checks you will see include:

• Setup time violations (maximum delay)
• Hold time violations (minimum delay)
• Clock skew violations (where a maximum skew constraint is set)
• Propagation delay violations
• Pulse width violations
• Recovery and removal violations
• External delay (input and output delay) violations
• Transition, capacitance and fanout violations (design rule checks)

Timing analysis checks whether a design meets its timing requirements. The common violations are:

• Setup violations: data reaches a register's input too late, so it is not stable for the setup time before the capturing clock edge. The register may capture the wrong value or go metastable. Causes include long logic paths, slow cells, long wires and unfavourable clock skew.
• Hold violations: data changes too soon after the clock edge, before the hold time has passed, so the new value corrupts the one being captured. Causes are very short paths and skew where the capture clock arrives late. Hold does not depend on clock frequency.
• Clock skew violations: the clock reaches different registers at different times. Skew is not a violation in itself, since STA includes it in every setup and hold check, but many flows set a maximum skew target for clock tree synthesis and report where it is exceeded.
• Propagation delay violations: a path exceeds a specified maximum delay, typically a set_max_delay constraint on a combinational or interface path.
• Pulse width violations: a clock high or low pulse, or a pulse on an asynchronous pin, is shorter than the minimum the cell requires. Duty-cycle distortion in the clock tree is a common cause.
• Recovery and removal violations: these apply to asynchronous set and reset pins. Recovery is like setup: the reset must be released a minimum time before the next active clock edge. Removal is like hold: the reset must stay asserted a minimum time after the clock edge. Synchronising the reset release is the usual fix.
• Transition and capacitance violations: a net drives too much load or switches too slowly. These are design rules from the library and must be clean even if slack is positive.

Overall, the timing report helps designers find and fix these violations so the design functions correctly at its target frequency across all corners.

Q3: List the possible techniques to fix a timing violation

• Buffering: buffers drive loads that are too large for a logic cell to drive efficiently. A long net is split and buffers are inserted to improve the transition, which improves data path timing and reduces setup violations. To fix hold violations, buffers or delay cells are inserted to add delay to short data paths.
• Mapping: converts primitive logic cells in the netlist to technology-specific gates in the library on the timing-critical paths.
• Unmapping: converts technology-specific gates back to primitive logic on the critical paths so they can be re-optimised.
• Pin swapping: examines the slack on each input of the gates on the worst paths and swaps logically equivalent input nets, so the latest-arriving signal uses the fastest pin of the gate, without changing the function.
• Wire sizing: wider wires or non-default routing rules on critical nets lower resistance.
• Transistor (cell) sizing: assigns a drive strength from the library to each cell instance. A weak cell on a critical path is replaced by a stronger one to reduce delay.
• Re-routing: moving a net to faster, thicker upper metal layers or shortening its route.
• Placement updates: moving cells on a critical path closer together.
• Re-synthesis (logic transformations): re-optimising the logic of the path.
• Cloning: reduces the load on a heavily loaded cell by replicating it. The copy connects to the same inputs, and the fanout is split between the two.
• Useful skew: delaying the clock to a capturing register gives a setup-critical path more time, borrowed from the next stage.
• Logic restructuring: rearranging logic so the late-arriving signal passes through fewer levels.
• Removing false violations: correct false path and multicycle path constraints so the tool does not fix paths that are not real.

Some further techniques, with the conditions under which they work:

• Reducing the clock frequency fixes setup violations at the cost of performance. It does nothing for hold violations.
• Inserting delay elements fixes hold violations on short paths. Adding delay to a setup-critical path makes it worse, so delay cells are only added where setup slack allows.
• Moving logic closer to its source or destination reduces wire delay.
• Increasing drive strength reduces delay on heavily loaded nets.
• Re-architecting: adding pipeline stages or retiming registers across logic splits a long path.
• Register duplication separates a high-fanout register into copies placed near their loads.

No technique fits every violation. The right choice depends on whether the problem is setup or hold, whether delay is in cells or wires, and how much area and power headroom is left.

Q4: Give the linear time computation scheme for Elmore delay in an RC interconnect tree

An acceptable answer includes:

• The Elmore delay formula: T(s,t) is the sum, over every resistor R_i on the path from source s to sink t, of R_i times C_i, where C_i is the total capacitance in the subtree below that resistor. Equivalently, it is the sum over all node capacitances times the resistance shared between the path to that node and the path to t.
• An explanation of the terms in the formula.
• Something that shows it can be done in linear time ("lumped" or "shared" resistances, recursive calculation and so on).

The linear time scheme uses two traversals of the tree, each visiting every node once:

1. Bottom-up pass (post-order): for each node, compute the downstream capacitance Cdown(v) = C(v) + the sum of Cdown over its children.
2. Top-down pass (pre-order): set delay(source) = R_driver x Cdown(source), or zero for an ideal source. For each child u of v, connected by edge resistance R_u, delay(u) = delay(v) + R_u x Cdown(u).

Each pass touches each node and edge once, so the total work is O(n) for n nodes, and the delay to every sink comes out at once.

Worked example (illustrative values). An ideal source drives node 1 through 100 ohms; node 1 has 10 fF. Node 1 branches to node 2 (200 ohms, 20 fF) and node 3 (50 ohms, 30 fF).

Node	Cdown	Delay
1	10 + 20 + 30 = 60 fF	100 x 60 fF = 6 ps
2	20 fF	6 + 200 x 20 fF = 10 ps
3	30 fF	6 + 50 x 30 fF = 7.5 ps

The skew between sinks 2 and 3 is 2.5 ps. Note that ohms times femtofarads gives femtoseconds, so 6,000 fs = 6 ps.

Q5: Can we reduce the Elmore delay by changing the width of a wire segment?

Given a unit wire resistance r and a unit wire capacitance c, a wire segment of length l and width w has resistance rl/w and capacitance cwl. Can we reduce the Elmore delay by changing the width of a wire segment? Explain your answer.

Expected answer: for a single uniform wire, the delay due to the wire itself is independent of width, because w cancels. By scaling different segments by different amounts you can reduce the delay, for example wider segments near the root (which carry the current for everything downstream) and narrower segments near the leaves.

The algebra: the wire's own distributed Elmore delay is (rl/w) x (cwl) / 2 = rcl^2/2. The width has cancelled, so widening a lone wire makes resistance fall exactly as fast as capacitance rises.

Width matters once the driver and the load are included. With driver resistance Rd and load capacitance CL:

T = Rd(cwl + CL) + (rl/w)(cwl/2 + CL)

Widening the wire increases the first term (the driver sees more wire capacitance) and decreases the last term (the load is charged through less resistance). Setting the derivative to zero gives an optimum width w* = sqrt(r CL / (Rd c)). A strong driver and a heavy load favour a wider wire; a weak driver favours a narrow one.

In a tree, each segment sees a different downstream load, so tapering (wide near the source, narrow at the sinks) reduces delay below that of any single uniform width. In real processes fringe and coupling capacitance do not scale with width, so widening helps a little more than this simple model suggests.

Correction: an earlier version of this answer computed RC = cl^2/w and concluded that a wider wire always has lower delay. The product (l/w) x (cwl) is cl^2 (times r), with no w left, so that conclusion was wrong.

Q6: Extend the ZST-DME algorithm to embed a binary tree such that the Elmore delay from the root to each leaf is identical

Expected answer: a new procedure is needed for calculating the Elmore delay given a choice of merging points, instead of using only the total downstream wire length. The merging segment becomes a set of points with equal Elmore delay instead of equal path length. A relevant paper is "Low-Cost Single-Layer Clock Trees With Exact Zero Elmore Delay Skew" by Andrew B. Kahng and Chung-Wen Albert Tsao.

Background. DME stands for Deferred-Merge Embedding. Given a binary tree topology over the clock sinks, it builds a zero-skew tree (ZST) of minimum wirelength in two phases:

1. Bottom-up: for each internal node, compute a merging segment, the set of all locations where the two child subtrees can be joined with zero skew. In Manhattan geometry this is a segment at 45 degrees (a Manhattan arc). The decision of exactly where to place the node is deferred.
2. Top-down: starting at the root, pick a point on each merging segment that is closest to its parent's chosen point, fixing the actual locations.

The extension to Elmore delay. With a linear (path length) delay model, equal delay means equal wirelength to each side. Under Elmore delay, each subtree carries a delay t and a total capacitance C, and both must be tracked in the bottom-up pass. To merge subtree 1 (t1, C1) and subtree 2 (t2, C2) with a connecting wire of length e, place the tapping point at a fraction x of the way from subtree 1, where

x = [ (t2 - t1) + r e (C2 + c e / 2) ] / [ r e (c e + C1 + C2) ]

This equation, from Tsay's exact zero-skew work, makes the Elmore delays from the tapping point to both sides equal. If 0 <= x <= 1, the merging segment lies on the connecting wire. If x falls outside that range, one subtree is so much slower that the wire to the faster side must be elongated (snaked) to add delay, and the merging point sits at the slower subtree's root. After each merge, the new subtree's delay and capacitance are updated and passed upwards; the top-down embedding phase is unchanged.

Correction: an earlier version described ZST-DME as "Delay Matching Embedding" in a mesh network, with an averaging step. DME places clock routing over sink locations in the plane, not in a mesh, and zero skew is achieved exactly through the tapping point equation, not by averaging delays.

Q7: IPO (in-place optimisation) and its effect on area, congestion and timing slack

IPO tries to optimise design timing by buffering long wires, resizing cells, restructuring logic and so on. Explain how these IPO steps affect the quality of the design in terms of area, congestion and timing slack. (a) Why is this called "in-place optimisation"? (b) Why are the two IPO steps different? (c) Why are both used?

(a) It is called in-place because it works on an already placed (and sometimes routed) design incrementally, rather than re-running synthesis and placement from scratch. Most cells keep their positions; new or resized cells are put near the logic they replace and legalised with small local moves.

(b) The question is usually read in one of two ways, and both are worth covering:

• As two kinds of transform: buffering addresses long wire delays and high fanout, while resizing addresses slow cells. Buffering adds cells to split a wire; resizing swaps a cell for a stronger or weaker one with the same function.
• As two points in the flow: IPO after placement uses estimated (virtual or global-route) wires and can make larger changes; IPO after routing uses extracted parasitics, is more accurate, but must avoid disturbing the routing and so is limited to small changes.

(c) Both are used because they are complementary. Wire problems need buffering and cell problems need sizing; early IPO makes the big gains cheaply, and late IPO fixes what only accurate parasitics reveal.

Effect on design quality:

• Area: buffering adds cells and upsizing uses larger cells, so area normally rises. Tools recover some area by downsizing cells on paths with spare slack.
• Congestion: added buffers and larger cells consume placement sites and add pins to route, which raises local congestion. Modern tools apply congestion-aware optimisation to limit this.
• Timing slack: slack improves on the paths that are fixed, giving margin against process, voltage and temperature variation. Upsizing a cell also increases the load on its driver, so IPO can make other paths worse if applied without care.

Q8: Clocking and place-and-route flow

Consider the following steps:

• Clock sink placement
• Standard-cell global placement
• Standard-cell detailed placement
• Standard-cell ECO placement
• Clock buffer tree construction
• Global signal routing
• Detailed signal routing
• Bounded-skew (balanced) clock (sub)net routing
• Steiner clock (sub)net routing
• Clock sink useful skew scheduling (solving the linear program and so on)
• Post-placement (global routing based) static timing analysis
• Post-detailed routing static timing analysis

(a) As a designer of a clock distribution flow for high-performance standard-cell ASICs, how would you order these steps? Can some steps be used more than once, and others not at all? (b) List the criteria for assessing possible flows. (c) What were the three next-best flows you considered, and why do you prefer your answer?

(a) Basic flow

1. Standard-cell global placement
2. Post-placement STA
3. Clock sink useful-skew scheduling
4. Clock buffer tree construction that is useful-skew aware (compare associative skew)
5. Standard-cell ECO placement, to put the buffers into the layout
6. Steiner clock subnet routing at the lower levels of the clock tree (following the CTGen type approach)
7. Bounded-skew clock subnet routing at all higher levels of the tree, and at lower levels where needed to enforce useful skews
8. Global signal routing
9. Detailed signal routing
10. Post-detailed routing STA

(b) Criteria

1. Likelihood of convergence at maximum clock frequency.
2. Minimum CPU time, by maximising incremental steps, minimising detailed steps and minimising iterations.
3. A good trade-off between wiring-based skew control and wire cost, which suggests Steiner routing at lower levels and bounded-skew routing at higher levels.

Comment 1: criteria not addressed here include power, insertion delay, and variant flows for hierarchical or gated clocking.
Comment 2: I do not know of any technology for clock sink placement that can separate it from placement of the remaining standard cells, so this flow does not invoke that step. I also do not want post-route ECOs.

(c) Variants considered

1. Add a step 11 that loops over steps 3 to 10. Not adopted, because the cost-benefit ratio was unattractive, and the trial placement and global routing already drive useful-skew scheduling, buffer tree construction and ECO placement.
2. After steps 1 to 4, re-place the entire netlist (global and detailed placement) and skip step 5. Not adopted, because the benefit of avoiding ECO placement and reusing a good clock skeleton was felt to be small: the buffer tree largely reflects the netlist structure, and re-placing can break the assumptions made in steps 3 and 4.
3. Iterate the first five steps: clock sink placement, ECO placement for legalisation, then incremental standard-cell global and detailed placement. Not adopted, because any objective for standalone clock sink placement would be very fuzzy, for example based on the overlap of the fan-in and fan-out cones of sequentially adjacent flip-flops.

An alternative answer, and how to judge it

A second possible ordering puts clock sink placement first, then global placement, clock buffer tree construction, bounded-skew and Steiner clock routing, useful skew scheduling, detailed placement, global and detailed signal routing, post-placement STA, ECO placement and finally post-route STA. Its listed criteria are timing, area, power, congestion, scalability and design rule compliance, and its three variants are a clock-first flow, a timing-driven flow and a congestion-driven flow.

It is weaker than the basic flow on two points an interviewer will notice. Useful skew scheduling comes after the clock tree is routed, so the tree cannot be built to deliver the scheduled skews. And post-placement STA is run after detailed routing, so the earlier steps have no timing data to guide them. It does correctly add power as a criterion and notes that ECO placement can be repeated, which the basic flow leaves out.

Q9: If we migrate to the next technology node and double the gate count, how would the size of the LEF and routed DEF files change?

LEF (Library Exchange Format) describes the technology and the library: routing layers, vias, design rules, and an abstract of each standard cell and macro (size, pins and blockages). It does not list the instances in the design, so doubling the gate count with the same library leaves the LEF essentially unchanged. Migrating to a new node can still make the LEF larger, because newer nodes add metal layers, more via definitions and many more spacing and patterning rules, and libraries may hold more cell variants. That growth comes from the technology, not from the gate count.

Routed DEF (Design Exchange Format) describes this particular design: every placed component, every pin, every net and the routed wire and via geometry of each net. Its size scales roughly with the number of instances and nets, so doubling the gate count roughly doubles it. It may grow somewhat more than 2x because:

• more metal layers mean more layer changes and vias per route;
• a larger design has some longer global nets with more segments;
• finer manufacturing grids can mean larger coordinate values in database units;
• power grids, fill and special nets also scale with die size.

A strong answer makes the distinction explicit: LEF tracks the library and process, DEF tracks the design.

Correction: an earlier version said both files grow because there are more gates to represent in the LEF. Gate count affects the DEF, not the LEF.

How interviewers probe these topics

• After Q2 and Q3, expect "which of those fixes help setup, which help hold, and which hurt the other?"
• After Q4, expect to compute Elmore delay by hand on a three- or four-node tree, as in the example above.
• After Q5, expect "why are upper metal layers thicker?" and "what about coupling capacitance?"
• After Q7, expect a question on how a resized cell changes its driver's delay.
• After Q9, expect "what does a .lib file hold that LEF does not?" (timing and power, not geometry).

FAQ

Is Elmore delay accurate enough for sign-off?

No. Elmore delay is the first moment of the impulse response and is an upper bound on the 50% delay for RC trees, which makes it useful for clock tree construction and optimisation. Sign-off timing uses extracted parasitics with more accurate delay calculation.

What is the difference between recovery and setup time?

They are the same kind of check applied to different pins: setup applies to the data input, recovery to the release of an asynchronous set or reset.

Why does slowing the clock not fix hold violations?

The hold check compares the launch and capture of the same clock edge, so the clock period does not appear in it.

Corrections made in this update

• Q2: recovery time was described as data stability after the clock edge; it is the asynchronous reset release check, the counterpart of setup.
• Q3: inserting delay was described as a general timing fix; it fixes hold and worsens setup. Clock gating was removed from the list of timing fixes, as it is a power technique.
• Q4: the earlier step-by-step method and formula were not the Elmore delay; replaced with the standard two-pass linear-time method.
• Q5, Q6, Q7 and Q9: corrected as noted under each question.