Top 50 CPU Architecture Interview Questions with Answers

These are 50 CPU architecture interview questions that come up again and again for processor design, verification, embedded and systems roles, each now followed by a short, accurate answer. They cover the basics (microprocessor vs microcontroller, fetch-decode-execute, RISC vs CISC), performance techniques (pipelining, superscalar and out-of-order execution, branch prediction, caches) and the system level (virtual memory, interrupts, DMA, multi-core). Use the answers as a starting point and be ready to go one level deeper on any of them.

Key takeaways

• Interviewers test whether you can explain why a technique improves performance and what it costs (area, power, complexity, security), not just define it.
• Pipelining, superscalar issue, out-of-order execution and speculation all exist to raise instructions per cycle (IPC); caches, prefetching and TLBs exist to hide memory latency.
• Know the three core equations: CPU time, average memory access time (AMAT) and Amdahl's law. They are listed in a short section after the questions.
• Some questions overlap (21 and 29 on speculation, 33 and 34 on the program counter); a good answer says so and explains the naming.
• A few topics are historical (northbridge and southbridge, MMX); answer them, then say how modern systems do it.

The questions keep their original numbering. Earlier versions of this post invited readers to post answers in the comments; short model answers are now given under each question, and you are still welcome to add your own answers or follow-up questions in the comments.

CPU fundamentals and organisation (questions 1 to 10)

1. What is the difference between a microprocessor and a microcontroller?

A microprocessor is mainly the CPU on a chip; memory and most peripherals are external. A microcontroller integrates the CPU with on-chip flash, SRAM, timers, ADCs and communication interfaces, so it can run a dedicated control task on its own. Microprocessors target general-purpose performance; microcontrollers target low cost, low power and real-time control.

2. What are the different components of a CPU, and how do they interact?

The main parts are the control unit, the datapath (ALU, shifter, floating-point and vector units), the register file, and the memory interface (load/store unit, caches, MMU and bus interface). The control unit decodes each instruction and steers operands from registers through the execution units, and results back to registers or memory.

3. How does pipelining improve CPU performance?

Pipelining splits instruction processing into stages (for example fetch, decode, execute, memory, write-back) separated by registers, so several instructions are in flight at once. It does not shorten one instruction's latency, but it raises throughput towards one instruction per cycle and allows a higher clock frequency. Its limits are hazards: structural (shared resource), data (an instruction needs a result not yet written, handled by forwarding or stalls) and control (branches, handled by prediction or flushing).

4. Explain the fetch-decode-execute cycle in a CPU.

The CPU fetches the instruction at the address in the program counter, decodes it to find the operation and operands, executes it (ALU operation, address calculation or branch), accesses memory if it is a load or store, and writes the result back. The program counter then moves to the next instruction or to a branch target.

5. What is the role of the control unit in a CPU?

The control unit decodes instructions and generates the control signals that select ALU operations, register reads and writes, memory accesses and the next program counter value. It can be hardwired (fixed logic, typical of RISC designs) or microprogrammed (control words stored in a microcode ROM, common in classic CISC designs). It also handles stalls, flushes, interrupts and exceptions.

6. What is the difference between Harvard and Von Neumann architectures?

Von Neumann uses one memory and one bus for both instructions and data, which is simple but creates a bottleneck because instruction fetch and data access compete. Harvard uses separate instruction and data memories and buses, so both can happen in the same cycle. Most modern CPUs are modified Harvard: separate L1 instruction and data caches backed by a unified memory.

7. What is cache memory, and how does it work?

A cache is a small, fast SRAM close to the core that holds recently used copies of main memory in fixed-size lines (commonly 64 bytes). It relies on temporal and spatial locality. Each access compares the address tag with the tags in the selected set; a match is a hit, otherwise the line is fetched from the next level. Key design choices are size, line size, associativity, replacement policy (for example LRU) and write policy (write-back or write-through).

8. How does virtual memory help in CPU performance?

Virtual memory gives each process its own address space, mapped to physical memory in pages by page tables. Its main benefits are isolation, protection and the illusion of a larger memory than is installed; it lets the operating system run many programs safely and load only the pages in use. It adds translation overhead, which the TLB hides, so the performance gain is at system level (more programs, efficient memory sharing) rather than faster single instructions.

9. What is the difference between CISC and RISC architectures?

CISC (for example x86) has many instructions of variable length, some of which work directly on memory and take many cycles. RISC (for example Arm, RISC-V) has fewer, fixed-length instructions, a load/store model where only loads and stores touch memory, and many general-purpose registers, which makes pipelining easier. Modern x86 cores decode CISC instructions into RISC-like micro-operations internally, so the difference today is mostly in the instruction set, not the core design.

10. Explain the role of a memory management unit (MMU) in a CPU.

The MMU translates virtual addresses to physical addresses using page tables, checks access permissions (read, write, execute, user or kernel), and raises a page fault when a translation is missing or an access is not allowed. It contains the TLB and usually a hardware page-table walker.

Parallelism, control flow and performance (questions 11 to 21)

11. What is the difference between parallel and serial processing?

Serial processing executes one operation after another. Parallel processing executes several at the same time, at instruction level (pipelining, superscalar), data level (SIMD) or thread and task level (multi-threading, multi-core). Parallel processing raises throughput but needs independent work and coordination between the parallel parts.

12. What is SIMD, and how does it work?

Single Instruction, Multiple Data: one instruction operates on several data elements packed into a wide vector register, for example adding eight 32-bit values in a 256-bit register in one operation. It suits image, audio, signal processing and machine learning workloads. Examples are x86 SSE and AVX, Arm NEON and SVE, and the RISC-V vector extension.

13. What is SMT, and how does it differ from SIMD?

Simultaneous multithreading (Intel calls its version Hyper-Threading) lets one core issue instructions from two or more hardware threads in the same cycle, sharing execution units to fill slots one thread would leave idle. SMT exploits thread-level parallelism across independent instruction streams; SIMD exploits data-level parallelism within one instruction stream.

14. What is the role of the ALU in a CPU?

The arithmetic logic unit performs integer arithmetic (add, subtract, compare, often multiply) and logical operations (AND, OR, XOR, NOT, shifts in many designs). It also produces status flags such as zero, carry, negative and overflow that branches use.

15. What is the difference between a register and a memory location?

Registers are a small set of storage elements inside the CPU, named directly in instructions and accessed in a cycle or less. Memory locations are addressed by number, sit in caches or DRAM, and take from a few cycles (L1 hit) to hundreds of cycles (DRAM) to reach. Registers are not addressable by memory pointers.

16. How does the CPU handle interrupts?

When an interrupt is signalled and enabled, the CPU finishes or cancels the instructions in flight to reach a precise point, saves the program counter and status, switches to a privileged mode, and jumps to a handler found through the interrupt vector table. The handler services the device and returns with a return-from-interrupt instruction that restores the saved state. Interrupt controllers (for example Arm GIC or NVIC, x86 APIC) prioritise and route requests.

17. What is a system call, and how is it handled by the CPU?

A system call is a request from a user program to the operating system kernel, for example to read a file. The program executes a dedicated instruction (syscall on x86-64, SVC on Arm, ECALL on RISC-V), which traps into kernel mode at a fixed entry point. The kernel checks the arguments, performs the service and returns to user mode.

18. What is branch prediction, and how does it improve CPU performance?

A branch predictor guesses the direction and target of a branch before it is resolved so that fetch can continue without waiting. Predictors range from simple 2-bit saturating counters to history-based designs such as gshare, tournament and TAGE predictors, with a branch target buffer for targets and a return address stack for returns. A misprediction flushes the wrong-path instructions, costing roughly the pipeline depth in cycles, so accuracy matters more as pipelines get deeper.

19. How does superscalar execution differ from pipelining?

Pipelining overlaps different stages of successive instructions, giving at most one instruction per cycle. Superscalar execution adds multiple parallel pipelines or execution units so that two or more instructions can be fetched, issued and completed in the same cycle, allowing IPC above one. Modern cores are both pipelined and superscalar.

20. What is out-of-order execution, and how does it work?

Out-of-order execution lets instructions run as soon as their operands are ready instead of strictly in program order. Registers are renamed to remove false dependencies, instructions wait in reservation stations or an issue queue, execute when ready, and retire in program order from a reorder buffer so that exceptions stay precise. The classic reference algorithm is Tomasulo's.

21. How does speculation help in CPU performance?

Speculation means doing work before it is known to be needed, mainly executing past an unresolved branch along the predicted path. If the guess is right, the work is already done; if wrong, the results are discarded and execution restarts on the correct path. It keeps a deep, wide pipeline busy. See also question 29.

Clocks, caches and the memory system (questions 22 to 30)

22. What is the role of the clock signal in a CPU?

The clock synchronises the sequential logic: flip-flops and pipeline registers capture new values on clock edges, so each pipeline stage has one clock period to finish its logic. The clock period must cover the slowest register-to-register path plus setup time and clock uncertainty.

23. How does clock speed affect CPU performance?

CPU time equals instruction count times cycles per instruction times clock period. A higher clock speed shortens the period, but performance only scales if CPI does not rise: memory latency stays fixed in nanoseconds, so it costs more cycles at higher frequency, and deeper pipelines raise branch penalties. Power also rises roughly with frequency times voltage squared, which is why clock speeds have grown slowly since the mid-2000s and designers focus on IPC and core count instead.

24. What is a cache miss, and how is it handled?

A miss occurs when the requested line is not in the cache. The cache requests the line from the next level, may evict a victim line (writing it back if it is dirty), fills the line and returns the data. Misses are classified as compulsory (first access), capacity (cache too small) and conflict (too many lines map to the same set). Non-blocking caches track outstanding misses in miss status holding registers (MSHRs) so other accesses can continue.

25. What is the difference between L1, L2, and L3 cache?

L1 is the smallest and fastest (tens of kilobytes, a few cycles), usually split into instruction and data caches and private to each core. L2 is larger and slower (hundreds of kilobytes to a few megabytes), usually private per core or per cluster. L3 is larger again (many megabytes), slower, and usually shared by all cores as the last-level cache. Exact sizes vary widely between products.

26. How does cache coherence work in a multiprocessor system?

Coherence ensures that all cores see a single, up-to-date value for each memory location even when copies sit in several private caches. Snooping protocols broadcast requests on a shared bus or ring; directory protocols track which caches hold each line, which scales better. Lines carry states such as Modified, Exclusive, Shared and Invalid (MESI, with variants such as MOESI and MESIF); a write invalidates other copies before it proceeds.

27. What is DMA, and how does it work?

Direct memory access lets a peripheral or a DMA controller move data between a device and memory without the CPU copying each word. The CPU programs source, destination and length, the DMA engine performs the transfer as a bus master, and it raises an interrupt when done. The system must keep caches coherent with DMA traffic, either in hardware or by cache maintenance in software.

28. What is prefetching, and how does it improve CPU performance?

Prefetching brings data or instructions into the cache before they are requested, hiding memory latency. Hardware prefetchers detect sequential and strided patterns; software prefetch instructions let the compiler or programmer give hints. Prefetching that is inaccurate or too early wastes bandwidth and can evict useful lines.

29. What is speculation, and how does it improve CPU performance?

This repeats question 21, so a good answer widens it. Besides branch speculation, CPUs speculate on memory dependences (running a load before older stores whose addresses are unknown) and sometimes on values. All speculative work is held in buffers and committed only when confirmed, then squashed if wrong. Since the Spectre and Meltdown disclosures in January 2018, interviewers also expect you to know that speculative execution can leak data through cache side channels, and that mitigations cost performance.

30. What is the difference between a hard and a soft fault?

In memory management, a soft (minor) page fault means the page is already in physical memory but not mapped for this process, so the OS only updates the page table; a hard (major) page fault needs the page to be read from disk, which is far slower. In hardware reliability the terms mean something else: a hard fault is a permanent defect, while a soft fault or soft error is a transient upset, for example a bit flip from a particle strike, which ECC or parity can detect and correct. Clarify which meaning the interviewer wants.

Data transfer, registers and system organisation (questions 31 to 40)

31. What is the difference between synchronous and asynchronous data transfer?

Synchronous transfer uses a shared clock, or a clock sent with the data, to time each transfer, as in SPI or a synchronous DRAM bus. Asynchronous transfer has no shared clock and relies on handshakes (request and acknowledge) or start and stop bits, as in a UART. Crossing between unrelated clock domains needs synchronisers or asynchronous FIFOs.

32. What is the difference between a stack and a queue?

A stack is last-in, first-out: push and pop happen at the same end. A queue is first-in, first-out: items enter at the tail and leave from the head. CPUs use a stack for function calls, return addresses and local variables; queues and FIFOs appear in hardware as instruction queues, store buffers and bus interfaces.

33. What is the role of the instruction pointer in a CPU?

The instruction pointer holds the address of the next instruction to fetch. "Instruction pointer" (IP, EIP, RIP) is the x86 name for what most other architectures call the program counter, so questions 33 and 34 describe the same register.

34. What is the role of the program counter in a CPU?

The program counter holds the address of the instruction being fetched. It normally advances by the instruction size, and branches, jumps, calls, returns, interrupts and exceptions load it with a new address. In a pipelined CPU each stage carries the PC of its own instruction, so the "PC" value depends on where you look.

35. How is the CPU connected to other components of a computer system?

Through a hierarchy of interconnects: an on-chip network or bus (for example Arm AMBA AXI or a ring or mesh) links cores, caches and the memory controller; the memory controller drives DDR or LPDDR DRAM; and I/O links such as PCI Express, CXL, USB and SATA connect devices, often through a separate chipset or I/O die.

36. What is the role of a northbridge and a southbridge in a computer system?

In older PC designs the northbridge connected the CPU to fast devices (memory and graphics) and the southbridge handled slower I/O (USB, SATA, audio, legacy buses). Note (November 2026): from the mid-2000s (AMD in 2003, Intel in 2008) the memory controller and graphics link moved into the CPU itself, and the remaining southbridge functions became a single chipset (for example Intel's Platform Controller Hub), so a modern answer should mention this change.

37. What is the difference between big-endian and little-endian byte ordering?

Big-endian stores the most significant byte of a multi-byte value at the lowest address; little-endian stores the least significant byte there. For 0x12345678, big-endian memory reads 12 34 56 78 and little-endian reads 78 56 34 12. x86 and most Arm and RISC-V systems run little-endian; network protocols use big-endian byte order.

38. What is the difference between a user mode and a kernel mode?

Kernel (supervisor) mode can execute privileged instructions, access all memory and control hardware. User mode is restricted, so a faulty or malicious program cannot damage the OS or other programs. The CPU enters kernel mode only through controlled paths: system calls, interrupts and exceptions.

39. What is the difference between physical and virtual addresses?

A virtual address is what a program uses; a physical address is the actual location in DRAM or a device. The MMU translates virtual to physical, page by page, so two processes can use the same virtual address for different physical memory.

40. What is the difference between synchronous and asynchronous reset?

A synchronous reset is sampled on the clock edge like any other input, so it needs the clock to be running and adds logic to the data path. An asynchronous reset acts immediately, without the clock. Its release (de-assertion) must still meet recovery and removal timing, so designs normally use asynchronous assertion with synchronous de-assertion through a reset synchroniser.

Instructions, arithmetic and multi-core (questions 41 to 50)

41. How does a CPU implement hardware multitasking?

Multitasking is mainly done by the operating system, which uses a timer interrupt to switch between tasks and saves and restores their registers. The CPU supports it with privilege levels, the MMU for per-task address spaces, address space identifiers so the TLB need not be flushed on every switch, and sometimes hardware task switching (x86 had task state segments, little used today). Hardware multithreading such as SMT runs several threads at once in one core without OS context switches.

42. What is the difference between a stack pointer and a frame pointer?

The stack pointer always points to the current top of the stack and moves as data is pushed and popped. The frame pointer points to a fixed place in the current function's stack frame and stays constant during the function, which makes locals and arguments easy to address and helps debuggers walk the call stack. Compilers often omit the frame pointer to free a register.

43. What is the difference between a direct and an indirect jump?

A direct jump encodes its target in the instruction, usually as a PC-relative offset, so the target is known at decode. An indirect jump takes its target from a register or memory, as in function pointers, virtual calls, switch tables and returns. Indirect jumps are harder to predict and need a target predictor or return address stack.

44. What is the difference between a barrel shifter and a shift register?

A barrel shifter is combinational logic, built from layers of multiplexers, that shifts or rotates a word by any number of bit positions in a single operation. A shift register is sequential: a chain of flip-flops that moves data one position per clock cycle, used for serial-to-parallel conversion, delays and scan chains.

45. What is the role of the MMX and SSE instructions in a CPU?

MMX (1997) and SSE (from 1999) are x86 SIMD instruction set extensions: MMX added packed integer operations on 64-bit registers, and SSE added 128-bit XMM registers with packed single-precision floating point, later extended to doubles and integers in SSE2 onward. They speed up multimedia and signal processing. Note (November 2026): AVX, AVX2 and AVX-512 have since widened the vectors to 256 and 512 bits, and MMX is now legacy.

46. What is the difference between a signed and an unsigned integer?

An unsigned n-bit integer represents 0 to 2^n minus 1. A signed integer, almost always in two's complement, represents minus 2^(n minus 1) to 2^(n minus 1) minus 1, with the top bit as the sign. Addition and subtraction use the same hardware for both; the difference lies in comparisons, overflow detection (carry for unsigned, overflow flag for signed), right shifts (logical or arithmetic) and widening (zero or sign extension).

47. How is floating-point arithmetic implemented in a CPU?

A floating-point unit (FPU) implements the IEEE 754 formats, each value having a sign, a biased exponent and a significand. Addition aligns the exponents, adds the significands, normalises and rounds; multiplication multiplies significands and adds exponents. Modern FPUs are pipelined, often provide fused multiply-add, and handle special cases such as denormals, infinities and NaN. Division and square root usually use iterative algorithms.

48. What is the difference between a single-core and a multi-core CPU?

A single-core CPU has one processing core. A multi-core CPU places several cores on one chip, usually with private L1 and L2 caches and a shared last-level cache, kept coherent by hardware. Multi-core raises throughput for parallel workloads within a power budget, but a single-threaded program gains nothing unless it is parallelised; Amdahl's law sets the limit.

49. What is the role of the TLB in a CPU?

The translation lookaside buffer caches recent virtual-to-physical page translations so the MMU does not have to walk the page tables on every access. A TLB miss triggers a page-table walk in hardware or software. Large pages (for example 2 MB) let each TLB entry cover more memory.

50. What is the difference between a fault and a trap?

Both are synchronous exceptions caused by an instruction. A fault is reported before the faulting instruction completes, and the saved PC points to that instruction so it can be restarted after the handler fixes the cause, as with a page fault. A trap is reported after the instruction completes, and the saved PC points to the next instruction, as with a breakpoint or system call instruction. This terminology comes from x86; other architectures group them all as exceptions.

Core formulas to know

• CPU time = instruction count x CPI x clock period (or divided by clock frequency).
• Average memory access time (AMAT) = hit time + miss rate x miss penalty, applied level by level through the cache hierarchy.
• Amdahl's law: overall speedup = 1 / ((1 minus f) + f / s), where f is the fraction of time that is improved and s is the speedup of that fraction. With f = 0.9 and unlimited cores, the speedup cannot exceed 10.
• Dynamic power is roughly proportional to activity x capacitance x voltage squared x frequency, which is why voltage and frequency scaling (DVFS) is so effective.

Test yourself: worked numbers

Interviewers often follow a definition with a quick calculation. Try each one before reading the answer.

Cache address breakdown

Question: a 32 KB, 8-way set-associative L1 data cache has 64-byte lines and a 32-bit physical address. How many sets are there, and how many offset, index and tag bits?

Answer: lines = 32,768 / 64 = 512; sets = 512 / 8 = 64. Offset = log2(64) = 6 bits, index = log2(64) = 6 bits, tag = 32 minus 6 minus 6 = 20 bits. A useful follow-up: with 4 KB pages, offset plus index is 12 bits, exactly the page offset, so the cache can be indexed with the virtual address while the TLB translates the tag in parallel (a virtually indexed, physically tagged cache with no aliasing).

Average memory access time

Question: L1 hit time is 1 cycle with a 5% miss rate; L2 hit time is 10 cycles with a 20% local miss rate; DRAM costs 200 cycles. What is the AMAT?

Answer: L2 miss penalty seen by L1 = 10 + 0.2 x 200 = 50 cycles, so AMAT = 1 + 0.05 x 50 = 3.5 cycles. Halving the L2 miss rate to 10% gives 1 + 0.05 x 30 = 2.5 cycles, which shows why last-level cache size matters so much.

Branch misprediction cost

Question: a core has a base CPI of 1.0. Branches are 20% of instructions, the predictor is 90% accurate and a misprediction costs 15 cycles. What is the effective CPI?

Answer: CPI = 1.0 + 0.2 x 0.1 x 15 = 1.3, a 30% slowdown. Raising accuracy to 95% gives 1.15. This is why deep pipelines need very accurate predictors.

Amdahl's law

Question: 80% of a program's run time parallelises perfectly. What speedup do 4 cores give, and what is the limit with unlimited cores?

Answer: 1 / (0.2 + 0.8 / 4) = 1 / 0.4 = 2.5x on 4 cores. With unlimited cores the limit is 1 / 0.2 = 5x.

To see whether a workload is limited by compute or by memory bandwidth on a given processor, try the roofline performance model tool on The Semiconductor Hub.

What interviewers are really testing

• Trade-offs, not definitions. For any feature (deeper pipeline, bigger cache, more associativity, SMT) expect "what does it cost?" The answer usually involves area, power, clock frequency, verification effort or security.
• Corner cases. What happens to an interrupt that arrives during a cache miss? How does a store to a line shared by another core proceed? How is a precise exception kept with out-of-order execution? The reorder buffer, store buffer and coherence protocol are the usual answers.
• Design and verification links. Design candidates are asked how a hazard is detected in hardware (comparing source and destination register numbers between stages). Verification candidates are asked how they would prove a feature works, for example random instruction streams compared against an instruction set simulator, and coverage of hazard combinations.
• Common slips. Saying pipelining reduces the latency of one instruction (it does not), confusing the TLB with the cache, mixing up write-back and write-through, and treating SMT as extra cores.

How to prepare

For each answer above, practise a follow-up: draw a 5-stage pipeline and show a load-use hazard, work out the set index and tag bits for a given cache, or trace a TLB miss through a page-table walk. The classic texts are Computer Organization and Design and Computer Architecture: A Quantitative Approach by John Hennessy and David Patterson. For more practice on this blog, try the pipelining interview question, the top 50 RTL design and micro-architecture interview questions, the introduction to semiconductor memories and the overview of RISC-V as an alternative to x86 and Arm. For a short definition, see the Semiconductor Hub glossary entry on pipelining.

Frequently asked questions

What CPU architecture topics are asked most often in interviews?

Pipelining and hazards, caches (mapping, misses, coherence), virtual memory and the TLB, branch prediction, out-of-order execution, RISC vs CISC and interrupts come up most. Design roles add timing, reset and clock domain questions; verification roles add how you would test each feature.

Is the instruction pointer the same as the program counter?

Yes. Instruction pointer is the x86 name (IP, EIP, RIP) and program counter is the name used by most other architectures. Both hold the address of the next instruction to be fetched.

Why do modern CPUs use both pipelining and superscalar execution?

Pipelining raises clock frequency and keeps each unit busy; superscalar issue lets more than one instruction finish per cycle. Together with out-of-order execution they raise IPC, while caches and prefetching keep the pipeline supplied with data.

Which books help with CPU architecture interviews?

Computer Organization and Design (Patterson and Hennessy) covers the fundamentals, and Computer Architecture: A Quantitative Approach (Hennessy and Patterson) goes deeper into out-of-order execution, memory hierarchy and multiprocessors.