For the last two years the hardest thing to get in AI hardware was not the chip itself but the package around it. TSMC's CoWoS capacity has decided how many accelerators can ship. Now TSMC is reported to be weighing another price rise for that packaging, and on 2 November 2026 Marvell agreed to buy Lumentum for about $115 billion to get into optical interconnect. Together they show where the bottleneck is moving: from packaging to the links between chips, boards and racks.
This post explains why AI chips depend on advanced packaging, what limits CoWoS, why copper wiring is running out of reach, and how pluggable, linear-drive and co-packaged optics compare.
Key takeaways
- AI accelerators need 2.5D packaging, such as TSMC's CoWoS, to place the processor next to its HBM memory with a very wide, short connection.
- TSMC is reported to be weighing a CoWoS price rise of up to 20% and wafer price rises of 3% to 6% from January 2027, mostly on 2 nm and 3 nm.
- As data rates rise to 200 Gb/s per lane and beyond, passive copper links reach only a metre or two, so more of the network inside AI clusters must move to optics.
- Marvell's all-stock deal for Lumentum (4.5 Marvell shares per Lumentum share, closing in the first half of 2028) combines interconnect chips with lasers and optical components.
- Co-packaged optics can cut network power, but vendor efficiency claims vary widely, and serviceability and yield are still open questions.
Why AI chips need advanced packaging
An AI accelerator spends much of its time waiting for data. To feed it, designers place six or more HBM stacks around the processor die and connect them with thousands of short wires. That connection is far too dense for an ordinary package substrate, so it runs through a silicon layer instead.
| Approach | How the dies connect | Typical use |
|---|---|---|
| CoWoS-S | A single large silicon interposer under all the dies | Earlier AI accelerators |
| CoWoS-L | Small local silicon bridges embedded in a redistribution layer, allowing packages larger than one interposer | Current large AI accelerators |
| Intel EMIB | Small silicon bridges embedded in an organic substrate | Intel products and foundry customers |
We compared these in detail in EMIB vs CoWoS and the 2026 PPAC decision guide.
What limits CoWoS capacity
- Package size keeps growing. Each new accelerator generation uses a larger interposer area and more HBM stacks, so each wafer of interposers makes fewer packages.
- Equipment lead times. Reports put lead times for some packaging tools at around eight months, which slows expansion.
- HBM supply. A CoWoS package is only useful if the HBM stacks for it exist, and those are sold out too. See our post on why packaging is now a primary design variable.
- Yield. A large package with many dies is only as good as its weakest die and bond, so known-good-die testing and assembly yield matter more than ever.
TrendForce estimates put TSMC's CoWoS output at more than 106,000 wafers in 2026, with plans to roughly double that in 2027. Even so, reports say TSMC is considering a price rise of up to 20%, which shows that demand is still ahead of supply.
Why copper runs out of reach
Inside a package the problem is density. Outside the package it is distance. Data moves between accelerators, switches and racks over serial links, and each step up in speed shortens how far a copper cable can carry the signal before it is lost in noise.
At 100 Gb/s per lane, passive copper cables can span a few metres inside a rack. At 200 Gb/s per lane (PAM4 signalling, about 106 GBd), the practical reach of passive copper falls to roughly a metre or two. Active copper cables with retimers extend this, at the cost of power and latency. Beyond that, the signal has to become light.
AI clusters make this worse, because tens of thousands of accelerators must talk to each other with high bandwidth and low latency. The more of that traffic leaves the rack, the more optics a data centre needs.
Three ways to bring optics closer
| Approach | Where the optics sit | Strengths | Trade-offs |
|---|---|---|---|
| Pluggable transceivers | In a module plugged into the front of the switch or server, with a DSP inside | Easy to replace, mature supply chain, 1.6T modules now in volume | The DSP and the long electrical path to the front panel use a lot of power |
| Linear-drive optics (LPO) | Still pluggable, but without a DSP; the host chip drives the optics directly | Lower power and latency than DSP-based modules | Tighter limits on the host's electrical signal and on interoperability |
| Co-packaged optics (CPO) | Optical engines inside the same package as the switch or processor die | Shortest electrical path, lowest power per bit | Harder to service, test and yield; a failed optical engine can mean replacing a whole switch |
Vendor figures show the potential but vary a lot. Explainers often quote 15 to 20 pJ/bit for pluggable optics and 5 to 7 pJ/bit for CPO. Broadcom and Cisco have claimed about 30% lower power for a 51.2 Tb/s switch with CPO, and NVIDIA has claimed several times better power efficiency for its silicon photonics switches. These are vendor claims, measured in different ways, so compare them with care. Our earlier post on co-packaged optics covers the technology in more depth.
What the Marvell and Lumentum deal signals
Under the agreement announced on 2 November 2026, Lumentum shareholders receive 4.5 Marvell shares for each Lumentum share, giving Lumentum an enterprise value of about $115 billion. Marvell brings electrical and optical interconnect chips, switching and custom silicon. Lumentum brings lasers, optical transceivers, optical circuit switches and compound semiconductor manufacturing. The companies expect more than $1 billion in annual synergies and plan to close in the first half of 2028, subject to approvals.
The engineering logic is that optical interconnect needs both sides: the DSPs, drivers and switch chips, and the lasers and photonic components. Owning both makes it easier to co-design optical engines for CPO and next-generation pluggables. Investors were less sure on the day, with both companies' shares falling.
What this means for chip and system designers
- Plan for optics early. If a product will use LPO or CPO, the host SerDes, package and thermal design all change. These are architecture decisions, not late additions.
- Budget for packaging cost and allocation. CoWoS-class packaging is a growing share of an accelerator's cost and lead time.
- Design for test. Large multi-die packages and co-packaged optics both make known-good-die and module-level test essential.
- Keep options open. Pluggable optics continue to improve, so a design that can use either pluggables or CPO reduces risk.
FAQ
Does co-packaged optics replace pluggable modules?
Not soon. CPO is starting in the largest AI switches, where power savings matter most. Pluggables will remain common for years because they are easy to replace and the supply chain is mature.
Why is packaging so expensive now?
The packages are huge, the equipment is scarce, and demand from AI is far ahead of capacity. Price rises are what a seller can charge in a tight market.
Is silicon photonics new?
No. It has been used in data centre transceivers for more than a decade. What is new is moving the optics into the package itself.
Figures in this post are as reported by the sources named on the date of writing, 3 November 2026. Packaging capacity and pricing figures are reports and analyst estimates, not TSMC disclosures, and optical power figures are vendor claims. Sources: Tom's Hardware and TweakTown (CoWoS pricing reports), TrendForce (CoWoS capacity), Marvell and Lumentum press release and SEC filings (deal terms), Broadcom, Cisco and NVIDIA (CPO claims).
Your comments will be moderated before it appears here.