DRAM prices have roughly doubled in 2026, high bandwidth memory (HBM) for 2027 is largely sold out, and phone and PC makers are paying for it. The cause is simple to state: every AI accelerator ships with stacks of HBM, and HBM uses far more wafer capacity per bit than ordinary memory. When the three big memory makers point their fabs at AI, everyone else gets less.
This post explains how HBM is built, why it squeezes the rest of the market, what the move to HBM4 changes, and what designers and buyers should plan for over the next two years.
Key takeaways
- Nikkei Asia reports that DRAM prices doubled during 2026 as memory makers gave priority to US hyperscalers.
- HBM stacks 8 to 16 DRAM dies on top of a base die and connects them with thousands of through-silicon vias (TSVs). It sits next to the processor on a silicon interposer.
- Per bit, HBM needs much more wafer area than standard DRAM because of bigger dies, TSV area, stacking yield loss and packaging. Every wafer moved to HBM removes several times more commodity bits from the market.
- TrendForce expects HBM contract prices to rise 70% to 140% in 2027, and Micron says most of its 2027 HBM volume is already committed.
- The knock-on effect is visible: smartphone shipments fell about 20% year on year in the third quarter of 2026, a drop linked to memory cost and supply.
What is happening
Three companies make nearly all of the world's DRAM: SK hynix, Samsung and Micron. Through 2026 they have shifted capacity towards HBM and high-capacity server memory for AI data centres. Nikkei Asia reports that DRAM prices doubled over the year and that PC makers are being squeezed. Samsung reported a record third-quarter profit on the back of memory pricing.
Looking ahead, TrendForce says HBM contract prices could rise 70% to 140% in 2027, although some long-term agreements cap the increase. Micron has said that much of its 2027 HBM volume is already sold. In China, Reuters reports that CXMT plans limited HBM3E production even though yields are said to be only 20% to 30%, a sign of how much demand there is for any HBM at all.
How HBM is built
Conventional DRAM sits in modules on the board, connected by a relatively narrow, fast bus. HBM takes the opposite approach: a very wide, slower-per-pin interface, placed millimetres from the processor.
| Part | What it does |
|---|---|
| DRAM core dies | Thinned DRAM dies stacked 8, 12 or 16 high. Each holds the memory cells and its share of the channels. |
| Through-silicon vias | Thousands of vertical copper connections through each die that carry data, power and control up and down the stack. |
| Base (logic) die | The bottom die. It handles the interface to the processor, test and repair. With HBM4 it is increasingly made on a logic process, sometimes by a foundry. |
| Microbumps and bonding | Join the dies to each other. Thermal compression bonding and mass reflow are used today; hybrid bonding is being developed for taller stacks. |
| Silicon interposer | Carries the very wide bus between the HBM stacks and the processor inside one package, for example in TSMC's CoWoS. See our explainer on silicon interposers. |
The interface width is the defining feature. HBM3 and HBM3E use 1,024 data lines per stack. The JEDEC HBM4 standard (JESD270-4) doubles that to 2,048, with up to about 2 TB/s per stack at its baseline pin rate. A modern AI accelerator carries six to eight stacks, so total memory bandwidth reaches several terabytes per second.
Why HBM squeezes everything else
The squeeze comes from how much silicon each HBM bit consumes. Four effects add up:
- Larger dies per bit. HBM dies carry TSV arrays and extra circuitry for the wide interface, so fewer bits fit in the same area than on a commodity DRAM die.
- Stack yield. A 12-high stack is only good if all twelve dies, the base die and every bond are good. One bad layer can scrap the whole stack.
- The base die. Each stack needs a logic die that holds no memory cells at all.
- Packaging capacity. Stacks must be bonded, tested and placed on interposers, which uses packaging capacity that is itself in short supply.
Micron has said in earnings commentary that HBM takes roughly three times the wafer capacity of standard DRAM per bit. The exact ratio varies by generation and maker, but the direction is clear.
A simple illustration (illustrative numbers, not data from any maker): imagine a fab with 100 units of wafer capacity, where 1 unit makes 1 unit of commodity DRAM bits or one third of a unit of HBM bits. If the maker moves 30 units to HBM, commodity supply falls by 30 units, but those wafers produce only 10 units' worth of HBM bits. The market loses 30% of its commodity bits to gain HBM bits equal to 10% of the old total. If demand for phones and PCs stays flat, prices for commodity memory must rise.
HBM3E to HBM4: what changes
| HBM3E | HBM4 | |
|---|---|---|
| Interface width per stack | 1,024 bits | 2,048 bits |
| Bandwidth per stack | Around 1.2 TB/s at the fastest pin rates | Up to about 2 TB/s at the JEDEC baseline; higher with faster pins |
| Stack height | 8 and 12 high | 12 and 16 high |
| Base die | Mostly made on the DRAM maker's own process | Moving to logic processes, with custom base dies possible |
Two consequences matter for capacity. The wider bus doubles the connections between memory and processor, which makes the interposer and packaging harder. And taller stacks make stack yield even more important, which is one reason hybrid bonding is being developed. Custom base dies also bring foundries into the memory supply chain for the first time, which adds another dependency.
Who feels it
- Phones. Semiconductor Today reports that smartphone shipments fell about 20% year on year in the third quarter of 2026, a drop linked to the memory crisis. Low and mid-range phones suffer most, because memory is a larger share of their bill of materials.
- PCs. PC makers face higher DRAM and SSD costs just as they want more memory for on-device AI features.
- Automotive and industrial. These buyers often need older DRAM types that makers are winding down, so allocation and end-of-life notices are a bigger risk than price alone.
- AI accelerator makers. Even the biggest buyers depend on HBM and packaging allocation, which now sets how many accelerators can ship.
What designers and buyers can do
- Design for the memory you can get. Support more than one memory type or density where possible, and keep alternative parts qualified.
- Use bandwidth more efficiently. Larger on-chip SRAM caches, data compression and better data reuse reduce how much external bandwidth a design needs. Our post on in-memory compute covers one research direction.
- Plan supply early. Long-term agreements, last-time buys for legacy DRAM and earlier forecasts to suppliers matter more in a tight market.
- Watch packaging, not only memory. HBM supply is limited by stacking and interposer capacity as much as by DRAM wafers.
What to watch through 2027
- How quickly new DRAM fabs and HBM lines from the three main makers come online.
- Whether CXMT and other Chinese makers can raise HBM yields enough to matter.
- Progress on hybrid bonding for 16-high stacks.
- Whether AI data centre spending keeps growing at the current pace. A slowdown would ease the squeeze quickly.
FAQ
Why not just build more DRAM fabs?
New fabs take two to three years and many billions of dollars, and the makers remember past price crashes caused by overbuilding. They add capacity carefully.
Is HBM only used in AI chips?
Mostly. High-performance computing, some networking chips and high-end FPGAs also use it, but AI accelerators take the bulk of supply.
Will DRAM prices fall again?
Memory has always been cyclical. Prices usually fall once new capacity arrives or demand slows, but most forecasts point to a tight market through at least 2027.
Market figures in this post are as reported by the sources named on the date of writing, 3 November 2026, and are not independently verified. Sources: Nikkei Asia (DRAM prices), TrendForce (HBM contract prices), Micron (HBM allocation and wafer intensity), Reuters (CXMT), Semiconductor Today (smartphone shipments), CNBC (Samsung results), JEDEC JESD270-4 (HBM4).
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