Backside Power Delivery: The Design Rules Nobody Warned You About

For more than fifty years, power and signals have shared the same side of the chip. Backside power delivery ends that. Power comes up through the back of a thinned wafer, and the front metal stack is left mostly to signals. Intel builds this into 18A as PowerVia, and TSMC plans it for A16 as Super Power Rail.

The headline benefit is easy to state: less voltage drop and more room for routing. The harder question for a design team is what changes in the flow, and what the change costs. That is what this post covers, with a small worked example you can redo using your own numbers.

Key takeaways

• Backside power shortens the path from the package to the transistor and frees front-side metal for signals.
• Intel reported more than 5% frequency improvement and more than 90% cell density on its PowerVia test chip. TSMC targets 8% to 10% more speed or 15% to 20% less power for A16 against N2P, with up to 1.10 times chip density. The TSMC figures are pre-production targets.
• Heat is the main trade-off. imec's simulations show that coarse power maps can make backside designs look cooler than frontside ones, while fine-grained workload maps show the opposite.
• Debug has to be replanned. Probing through the back of the die, a mainstay of silicon debug, no longer works in the old way.
• The gain is largest on high-current designs with congested routing. A low-current, thin-margin product has to work harder to justify it.

What actually moves

In a frontside design, current enters through package bumps and travels down the whole metal stack to reach the transistors. The thick top layers carry it well, but the last few thin layers have high resistance, and that is where much of the drop occurs. Those same layers are also the ones signal routing wants most.

A backside design thins the wafer until the transistor layer is close to the back surface, then builds a power network there. The two leading approaches connect to the transistors differently:

	Intel PowerVia (18A)	TSMC Super Power Rail (A16)
Connection to the device	Nano through-silicon vias from the back, landing on a contact level	Direct connection from the backside network to source and drain
Published results or targets	Test chip: more than 5% frequency improvement, more than 90% cell density	Targets against N2P: 8% to 10% speed, 15% to 20% power, up to 1.10 times density
Status of those figures	Measured on Intel's own test chip, built in 2023 with Intel 4 transistors	Announced in 2024. TSMC's annual report schedules volume production for the second half of 2026

These numbers come from different baselines and different designs, so they should not be compared directly. They do show what each company is claiming, and TSMC's framing is telling: it aims A16 at data center products with complex routing and dense power networks.

A worked example: what the voltage drop is worth

Vendor percentages are hard to apply to your own block, so here is a small model. Every number in it is an illustrative assumption, not data from any foundry. Replace them with your own.

Assumption	Frontside	Backside
Supply voltage	0.75 V	0.75 V
Block current	1 A	1 A
Effective on-die power path resistance	30 mΩ	18 mΩ
Static IR drop	30 mV (4.0% of supply)	18 mV (2.4% of supply)

You have recovered 12 mV, or 1.6% of supply. You can spend it in one of three ways:

1. Frequency. Keep the supply and sign off at a higher effective voltage. How much speed you gain depends on your library's sensitivity near that voltage, so read it from your own timing data.
2. Power. Lower the supply by up to 12 mV for the same speed. Dynamic power scales with the square of voltage, so 1.6% less voltage is roughly 3.2% less dynamic power.
3. Area and routing. Keep the same drop and relax the power grid. Freed front-side tracks can then lift utilisation or ease congestion.

You can only spend it once, and a real design will mix the three. The useful habit is to write down which one your product needs before you commit. If your block draws a tenth of this current, the same resistance change recovers only 1.2 mV, which may not repay the extra process steps. This is why the case is strongest for high-current compute.

The design rules that change

Here is how the flow changes, stage by stage. This is our reading of the published work, and your foundry's rule deck has the final word.

Stage	What changes	What to do about it
Architecture	Current density can rise, and heat concentrates differently	Run a thermal estimate with real workloads before fixing the floorplan
Power grid	Two networks to reason about, with far lower front-side need	Set an IR budget for each path and re-derive your electromigration limits
Standard cells	Power rails leave the cell or change form	Compare libraries on delivered utilisation rather than raw track height
Placement	Backside connections take space at the device level and create keep-outs	Include the connection pattern in congestion analysis early
Clock	Backside metal is attractive for low-resistance clock nets, and research is active on double-sided trees	Ask your foundry and tool vendor what is qualified before planning around it
Signal integrity	The power network no longer sits between the signal layers	Recheck shielding assumptions and return paths, which older rules took for granted
ESD	Protection paths change when rails move	Review the ESD network with your foundry from the start. imec has flagged this as an open challenge
Sign-off	Thermal and voltage now interact more strongly	Run coupled analysis, and do not sign off from separate corners alone
Package	Bumps connect to a different stack, and the thinned die handles differently	Involve the package team in floorplanning
Debug	Traditional optical access from the back is largely gone	Plan access points and on-chip visibility before tape-out

The thermal trap

This is the point most summaries skip. In a frontside chip, the silicon substrate under the transistors spreads heat sideways. A backside design removes most of it and puts a metal and dielectric layer there, which is a poorer lateral conductor. In its model, an imec-led study used 135 W/(m·K) for the thin silicon and 71 W/(m·K) for the backside layer.

The study's main lesson concerns method. With uniform power maps at 200 µm resolution, backside designs showed lower peak temperatures than frontside ones. With workload-based maps at 5 µm resolution, they showed consistently higher peaks. It also cites earlier work in which backside hotspots ran up to 14 °C above frontside in a 2D high-performance SoC.

So a coarse thermal estimate may tell you the wrong story, and in the reassuring direction. Our recommendation is simple: do not accept a backside thermal result unless you know the resolution of the power map behind it. The same study also found that backside metal layers partly offset the rise, so the backside stack is a thermal design variable as well as an electrical one.

Debug has to be designed in

For years, failure analysts reached transistors through the back of the die using light, with laser voltage probing and photon emission. Backside metal now blocks that route. Papers at the ISTFA failure analysis conference describe e-beam probing as the contactless alternative, including work on A16 gate-all-around devices, and flows that remove the backside metal stack layer by layer to reach the active layer. E-beam needs a line of sight, so access holes have to be planned.

Intel addressed this directly when proving out PowerVia, by building test chips with deliberately hidden bugs, and it reported acceptable debug times. The message for everyone else is that this is solvable, but it needs planning. Agree a debug plan with your failure analysis team before tape-out, covering which nets need to be reachable and how much on-chip visibility you need to make up for lost probe access.

Should your product use it?

Answer these five questions before the node decision is made:

1. Is voltage drop limiting you today? If you are not losing frequency to droop, the main gain is routing.
2. Is your routing congested in the lower metal? If it is, the freed tracks may matter more than the voltage.
3. What are your power density and workload pattern? Sharp, local activity is where the thermal penalty shows up.
4. Can your cooling and package absorb a higher hotspot? If the thermal margin is already gone, the gain may be throttled away.
5. Does your failure analysis partner have a backside flow? If not, schedule risk rises at the worst time, during first silicon.

Two or more strong yes answers on the first two questions, and no red flags on the last three, make a good case. If it is the other way round, the frontside version of the node may be the better buy. Our SoC lifecycle on The Semiconductor Hub shows where these decisions fall in a programme.

FAQ

Is backside power the same as a buried power rail?

No, though they are related. A buried power rail places the rail below the transistors, and it is one way to connect a backside network. Backside power delivery describes the whole network on the back of the wafer.

Does it make chips cheaper?

Not by itself. It adds wafer bonding, thinning and backside processing. The saving has to come from density, performance or power, which is why vendors aim it first at high-value compute.

Will signals move to the back too?

Research on double-sided clock trees is active. Treat this as something to watch, and check what your foundry has actually qualified.

Sources

• Intel, "With PowerVia, Intel Achieves a Chipmaking Breakthrough", 5 June 2023.
• TSMC, press release on the 30th North America Technology Symposium, 24 April 2024, and TSMC 2025 Annual Report.
• Chen et al. (imec, Politecnico di Torino), "Thermal Implications of Non-Uniform Power in BSPDN-Enabled 2.5D/3D Chiplet-based Systems-in-Package using Nanosheet Technology", arXiv:2508.02284, August 2025.
• imec, VLSI Symposium 2023 materials on backside power connections and ESD.
• Jiang et al., "A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis", arXiv:2503.12512, 2025.
• ISTFA 2025 and 2026 proceedings and abstracts on fault isolation for backside power silicon.

The worked example uses illustrative numbers. Vendor figures are the companies' own claims and targets, as published on the dates shown.