Displaying posts in the categoryClocking and CDC
Clocking and CDC articles
RTL Design
The hardest logic design interview questions are not about definitions. They describe a failure on a real chip, such as a FIFO that fails at speed, a register that flips on its own or a reset that will not release cleanly, and ask you to reason from symptom to cause to fix. Below are ten such questions, each with a model answer, the points a strong candidate covers and the follow-ups interviewers tend to ask. Anyone who has sat a semiconducto…
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Murugavel Ganesan
August 29, 2025
Verilog
To divide a 1 GHz clock down to an average of exactly 622.08 MHz with digital logic only, use a phase accumulator: add 1944 every input cycle, modulo 3125, and produce one output pulse each time the sum wraps. That works because 1000 / 622.08 reduces exactly to 3125 / 1944, so the output alternates between periods of one and two input cycles, the long-run average is exact, and every output edge stays within one input cycle of its ideal position.…
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Murugavel Ganesan
August 29, 2025
Verilog
The most common RTL coding mistakes come from forgetting that Verilog and VHDL describe hardware, not a program. Unsynchronised clock domain crossings, software-style code, accidental latches, incomplete resets, tangled state machines, thin simulation, missing timing constraints, hard-coded widths, unreadable code and unchecked synthesis output account for most of the bugs found in junior engineers' designs. Each one is avoidable with a fe…
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Murugavel Ganesan
June 09, 2025
Synthesis
A multi-cycle path is a timing path that the design intends to take more than one clock cycle, so static timing analysis (STA) should check it against a later capture edge. A false path is a path that can exist structurally but is never required to carry a change that must be captured in a given time, so STA should not time it at all. Both are timing exceptions: constraints that override the default single-cycle check. Set correctly, they stop t…
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Murugavel Ganesan
November 28, 2023
Tutorials
You decide on a clock network by starting from the chip's timing, power and variation budgets, then picking the cheapest distribution structure that meets them. A plain buffered clock tree, built by clock tree synthesis, suits most ASIC blocks. Balanced H-trees, fishbone (spine) structures and tree-driven meshes are used when skew, on-chip variation or very high frequency make a simple tree too risky, at the cost of more wire and power. Thi…
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Murugavel Ganesan
September 01, 2023
Physical Design
In this blog post, we will discuss some of the challenges and techniques involved in designing a clock network for a very large scale integration (VLSI) circuit. A clock network is a special type of interconnect that distributes the clock signal to all the synchronous elements in the circuit, such as flip-flops, latches, and registers. The clock signal is used to synchronize the operation of these elements and ensure correct functionality and ti…
Static Timing Analysis
Clock skew variation is the spread in clock skew between two flip-flops caused by process, voltage and temperature (PVT) variation, on top of the nominal skew the clock tree was designed for. It is estimated in three main ways: statistical models built from the delay spread of each clock buffer and wire, simulation across corners and Monte Carlo samples, and measurement on silicon. The estimate matters because every picosecond of skew variation …
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