Displaying posts in the categoryEDA Tools
EDA Tools articles
Verification
Until recently, an EDA budget was a negotiated number that stayed put for the length of a contract. AI agents change that, because they add two bills that move with use: model tokens, and the extra tool licences those agents consume when they run simulations by the hundred. Vendors and customers are now arguing openly about both. The public debate tends to quote a single token price, and a single price is no help to a manager planning next yea…
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Murugavel Ganesan
November 11, 2026
Top10
The semiconductor industry is adopting AI-assisted design tools faster than it is changing the teams that use them. The tools now help with RTL, verification, physical design, power and test, but hiring, job roles, training and performance metrics still reflect how chips were built a decade ago. That gap between 2026 tools and 2015 team structures is where expensive mistakes happen, and closing it is a leadership and organisational design task,…
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Murugavel Ganesan
June 24, 2026
Technology
A PDK (Process Design Kit) is the package of models, rules, libraries and verification decks that a foundry supplies for one manufacturing process, so that chip designers can simulate, lay out and check a design before it is built. It is the foundry's process described in a form that EDA tools can read. Every chip that reaches silicon, from a smartphone processor to a power converter, was designed against a PDK, which is why it is often call…
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Murugavel Ganesan
September 16, 2025
VHDL
The best free HDL simulators today are Icarus Verilog and Verilator for Verilog and SystemVerilog, and GHDL and NVC for VHDL. All four are open source and actively maintained. If you need a mixed-language or full SystemVerilog simulator at no cost, the free editions that ship with FPGA vendor tools (AMD Vivado's built-in simulator and Questa Altera FPGA Starter Edition) and the browser-based EDA Playground are the practical options. Free H…
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Murugavel Ganesan
March 19, 2023
VHDL
The best online VHDL resources today are a handful of long-lived tutorial sites (VHDL-Online, Doulos KnowHow, the UCR "Learn by Example" tutorial), a few classic free texts such as Ashenden's VHDL Cookbook, and free simulators you can run in a browser or on a laptop, such as EDA Playground, GHDL and NVC. Pair one tutorial with one good textbook and a free simulator, and write small designs from the first day. This page keeps the or…
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The Editor's Desk
January 08, 2014
EDA Tools
The electronic design automation (EDA) tool industry is big business, and commercial licenses are extremely expensive. Open standards have driven many proprietary EDA technologies to be publicly released as free/libre open source software (F/LOSS) and some have become IEEE standards. In this article, author Arthur Low reviews the history of key advances in ICs and EDA tools. The common theme presented in this article for the driver of technology…
Synthesis
The High Level Synthesis Blue Book is a comprehensive guide for designing hardware using C++. It is targeted to RTL designers that are currently using, moving, or planning to move, to an HLS design environment. Check the blog post by Thomas Bollaert and More here . The High-Level Synthesis Bluebook is available online by clicking here . Author Michael Fingeroff will also be hosting a free webinar on June 23rd where he will be presenti…
India Semiconductors
The conference schedule and the registration links can be found here . With a program that is focused on helping you deal effectively with every day design challenges, SNUG is committed to making the best possible use of your time and delivering practical information you can take away and apply to your current project as well as future designs. CLICK HERE to register in advance. If you cannot attend the full program, please register for the ses…
Signal Processing
VLSI Solution has announced VSIDE - the Integrated Development Environment for VSDSP Processor Family. VSIDE is an integrated development environment for VLSI Solution's 16/40-bit VSDSP digital signal processor family. It contains a complete set of development utilities, including an optimizing ANSI-C compiler, assembler, linker, profiler, etc. All programs are integrated into a simple-to-use, easy-to-learn package running on a PC / Windows …
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Murugavel Ganesan
May 13, 2010
Verification
Acceleration, Emulation, and FPGA prototypes are most talked about these days and each has a distinctive role to play. In our earlier post we reflected on the Cadence rollout of Palladium XP, a verification computing platform that unifies acceleration capabilities from the Incisive Xtreme product line with Incisive Palladium emulation, incorporating some of the strongest capabilities from each platform. You can read the press release her…
Verification
Cadence Design Systems, Inc. has announced a fully integrated high-performance verification computing platform, called Palladium XP, that unifies simulation, acceleration and emulation into a single verification environment. Developed to support next-generation designs, the highly scalable Palladium XP verification computing platform lets design and verification teams bring up their hardware/ software environment faster and produce better qualit…
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Murugavel Ganesan
April 27, 2010
Semiconductor Industry
The main VLSI conferences are ISSCC, the VLSI Symposium and CICC for circuit design, DAC, DATE, ICCAD and ASP-DAC for design automation, IEDM for devices, ITC and ETS for test, and ISLPED for low-power design. Around them sit dozens of regional and specialist meetings on SoCs, FPGAs, RF, asynchronous logic and hardware security. This list was first published in April 2010 (it used to be a sidebar widget and was moved into a post so it could be r…
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Murugavel Ganesan
April 14, 2010
Signal Processing
Taking a floating-point representation of an algorithm into a fixed-point representation is an integral step on the path towards implementation. Unfortunately, it is known to be time-consuming, tedious and error prone. This paper from synopsys describes proven methodologies on how to overcome the hurdles, including many useful tips to get you to results faster.
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Murugavel Ganesan
April 14, 2010
Static Timing Analysis
This application note from synopsys describes the advanced on-chip variation (OCV) solution in PrimeTime, including the recommended usage flow, and also provides an example script. The information described in this document is valid for PrimeTime versions starting with B-2008.12.
Verilog
Verilog2C++ is a Verilog to C++ translation program that translates a C++ class of a Verilog design using a cycle-accurate representation of each nets and registers. Verilog2C++ is about 10 times faster than other commercial simulators, but has only simple functions.
Verilog
Source Navigator for Verilog is full featured tool for editing and navigating through large projects with many Verilog files. It parses Verilog code into a database that can be used to navigate files, trace connectivity, and find modules and signals in the design. It can even parse your files as you edit so you don't launch those long compile scripts only to end up with a syntax error after 5 minutes of compiling. Source Navigator was dev…
Verilog
Comit-TX extracts a self-checking Verilog testbench of any module inside a design that has a system level testbench. Comit-TX, with the extracted testbench, enables the module's replacement to be verified in a stand-alone basis in an environment identical to its final working environment, without having to simulate the entire system.
Synthesis
With thousands of Tapeouts, Conformal ASIC is the most widely-supported equivalency checking tool in the industry. It's also production-proven with more physical design closure tools, advanced synthesis tools, ASIC libraries, and IP cores than any other formal verification tool. Many EDA tool vendors rely on Conformal ASIC as an independent standard within their regression suites to verify the results that their own tools produce. Key Feat…
EDA Tools
nECO is an integrated graphical netlist modification tool for the Verdi and Debussy debug systems. The Novas debug systems accelerate users' understanding of complex designs to improve design, verification, and debug productivity. nECO adds the ability to isolate logic that needs to be changed in a flattened schematic, make the necessary changes, and write the modified design to a new netlist file.
RTL Design
The Identify RTL Debugger lets FPGA designers and ASIC prototyping designers to functionally debug their hardware directly in their RTL source code. This allows functional verification with RTL designs 10,000 times faster than RTL simulators, and enables the use of in-system stimulus for applications like networking, audio and video, and HW/SW designs. Identify software allows designers to directly select signals and conditions in their RTL sour…
