Displaying posts in the categoryAI Hardware
AI Hardware articles
Semiconductor Economics
Google, Amazon, Meta and Microsoft all run their own AI accelerators now, and each publishes figures showing that its chip beats a GPU on cost or efficiency for its own work. It is easy to read that as proof that any large buyer should do the same. Those figures say nothing about what the programme cost or how many chips it took to pay that back. So this post builds the missing sum. It sets a merchant GPU against a custom part using fixed cost…
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Murugavel Ganesan
November 09, 2026
Semiconductor Business
Through HBM3E, the base die at the bottom of a memory stack was a memory maker's own part, built on its own process and sold inside a standard product. Custom HBM breaks that up. The memory controller can move from the host chip into the base die, a logic foundry makes the die, and a customer may want its own circuits in there as well. The technical case is well covered. The commercial one is not, because a part that used to have one owner…
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Murugavel Ganesan
November 08, 2026
Semiconductor Manufacturing
A processor can pass wafer sort, final test, system-level test and burn-in, go into a server, and then return a wrong answer from an ordinary instruction. No machine check fires and no log line appears. The program carries on with a bad number. Meta described one such case in which a CPU core calculated a file size as zero, and files went missing from a database as a result. Google, Meta and Alibaba have now published enough data to show that …
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Murugavel Ganesan
November 05, 2026
Process Technology
For more than fifty years, power and signals have shared the same side of the chip. Backside power delivery ends that. Power comes up through the back of a thinned wafer, and the front metal stack is left mostly to signals. Intel builds this into 18A as PowerVia, and TSMC plans it for A16 as Super Power Rail. The headline benefit is easy to state: less voltage drop and more room for routing. The harder question for a design team is what change…
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Murugavel Ganesan
November 05, 2026
Photonics
For the last two years the hardest thing to get in AI hardware was not the chip itself but the package around it. TSMC's CoWoS capacity has decided how many accelerators can ship. Now TSMC is reported to be weighing another price rise for that packaging, and on 2 November 2026 Marvell agreed to buy Lumentum for about $115 billion to get into optical interconnect. Together they show where the bottleneck is moving: from packaging to the links…
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Murugavel Ganesan
November 03, 2026
Special Reports
DRAM prices have roughly doubled in 2026, high bandwidth memory (HBM) for 2027 is largely sold out, and phone and PC makers are paying for it. The cause is simple to state: every AI accelerator ships with stacks of HBM, and HBM uses far more wafer capacity per bit than ordinary memory. When the three big memory makers point their fabs at AI, everyone else gets less. This post explains how HBM is built, why it squeezes the rest of the market, w…
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Murugavel Ganesan
November 03, 2026
Semiconductor Manufacturing
Originally published on LinkedIn . Advanced packaging is now one of the main ways the semiconductor industry improves system performance. As transistor scaling slows and gets more expensive, the gains increasingly come from how dies are split, stacked and connected inside one package. That makes packaging a design decision taken at the start of architecture work, not a step at the end of manufacturing. Packaging is no longer a footnote in sem…
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Murugavel Ganesan
August 27, 2026
Memory
In-memory compute (IMC) does the arithmetic inside the memory array instead of moving data out to a processor. For AI inference, the weights stay in place, the input activations drive the wordlines, and each bitline adds up the products, so the multiply-accumulate happens where the data lives. It matters because moving a number costs far more energy than computing with it: in published 45 nm figures, a 32-bit DRAM read costs about 640 pJ against…
by
Murugavel Ganesan
August 27, 2026
