Displaying posts in the categoryFPGA
FPGA articles
Tutorials
To benchmark an FPGA accelerator fairly, measure three things on the same realistic workload: performance (throughput, latency and speedup over a baseline), power and energy (measured at the board or wall, not only estimated), and accuracy (error against a trusted reference). Report them together, because an FPGA design can trade one against the others, for example by using lower-precision arithmetic to gain speed and save power at some cost i…
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Murugavel Ganesan
December 14, 2023
Tutorials
An FPGA accelerator is a board or device that uses a field-programmable gate array to run a specific task faster or more efficiently than a general-purpose processor. Instead of executing instructions, the FPGA is configured into a custom circuit for that one algorithm, with its own parallel datapaths and pipelines. Most FPGA accelerators sit beside a host CPU on a PCIe card and take over the heavy part of a workload, such as packet processing, …
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Murugavel Ganesan
December 13, 2023
Verilog
FPGA based cryptographic acceleration means moving encryption, decryption, hashing and signature work from a general-purpose processor into custom logic on a field-programmable gate array. The FPGA wins when the work is regular and highly parallel, such as AES on a 100 Gbit/s link or SHA-256 over a storage stream, because it can pipeline the algorithm and process a new block every clock cycle. It also stays reprogrammable, so the design can foll…
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Murugavel Ganesan
December 12, 2023
Tutorials
FPGA based video processing acceleration means building the video pipeline, such as scaling, filtering, codec stages or neural network inference, directly in programmable hardware instead of running it as software on a CPU or GPU. Because pixels can be processed as they stream in, an FPGA can deliver high, deterministic throughput with latency measured in video lines rather than frames, often at lower power than a general-purpose processor for t…
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Murugavel Ganesan
December 12, 2023
GPUs and Accelerators
FPGA based customised acceleration means moving the hot loop of an application out of software and into a hardware circuit built for that one job on a field-programmable gate array. Because the circuit is shaped around the algorithm, with its own parallel processing elements, on-chip memories and number formats, it can beat a general-purpose processor on throughput, latency and energy per operation for the right workloads. The trade-off is engin…
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Murugavel Ganesan
December 12, 2023
Tutorials
To design and implement an FPGA accelerator for a specific ML model, you define the model and its targets, profile it to find the compute and memory bottlenecks, design a parallel datapath and dataflow that fits the FPGA's DSP, memory and I/O resources, implement it in HLS or an HDL, verify it in simulation and on hardware, and then benchmark and tune it. The key to a good result is matching the hardware to the model: quantised arithmetic,…
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Murugavel Ganesan
December 10, 2023
Tutorials
FPGA based machine learning inference means running an already trained model on an FPGA, with the network's layers built as custom hardware pipelines instead of instructions on a CPU or GPU. The model is usually quantised to low-precision integers, mapped onto the FPGA's DSP blocks and on-chip memory either directly or through a programmable overlay engine, and connected to a host processor that sends inputs and collects results. The pay…
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Murugavel Ganesan
December 10, 2023
Tutorials
A multicycle path is a timing path between two registers on related clocks where the design intentionally gives the data more than one clock period to arrive. The logic is built so the destination only uses the value every N cycles, typically through a clock enable, so the default single-cycle check is too strict. You tell the timing tool about that intent with a multicycle path constraint, and you must adjust the hold check at the same time, or…
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Murugavel Ganesan
November 21, 2023
Semiconductor Business
In October 2023 Intel announced that its Programmable Solutions Group (PSG), the FPGA business it gained by buying Altera, would operate as a standalone business from 1 January 2024, with an IPO planned within two to three years. For the FPGA market this meant a focused second supplier competing with AMD's Xilinx business, still tied to Intel for manufacturing but free to set its own priorities. This article was written at the time of the …
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Murugavel Ganesan
October 25, 2023
