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Top10 articles
Top10
The semiconductor industry is adopting AI-assisted design tools faster than it is changing the teams that use them. The tools now help with RTL, verification, physical design, power and test, but hiring, job roles, training and performance metrics still reflect how chips were built a decade ago. That gap between 2026 tools and 2015 team structures is where expensive mistakes happen, and closing it is a leadership and organisational design task,…
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Murugavel Ganesan
June 24, 2026
Top10
Why learning AI prompting as a career skill is the wrong bet, and what to do instead How LinkedIn influencers mislead millions, and where the real opportunities in AI lie. Prompting is a useful everyday skill, but it is a poor thing to build a career on. It is easy to copy, it changes every time the models change, and the tools are increasingly doing it for you. The lasting value in AI sits in the layers around the prompt: data, integration…
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Murugavel Ganesan
August 26, 2025
Top10
Service roles in semiconductors are a strong career choice, not a fallback. A good design services firm puts an engineer on several chips, clients, tool flows and process nodes in the time a product engineer might spend on one block of one chip. That breadth builds skill, judgement and a network quickly. Product roles still offer depth, ownership and stability, so the right choice depends on what you want from the next three to five years. A co…
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Murugavel Ganesan
July 08, 2025
Verilog
The most common RTL coding mistakes come from forgetting that Verilog and VHDL describe hardware, not a program. Unsynchronised clock domain crossings, software-style code, accidental latches, incomplete resets, tangled state machines, thin simulation, missing timing constraints, hard-coded widths, unreadable code and unchecked synthesis output account for most of the bugs found in junior engineers' designs. Each one is avoidable with a fe…
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Murugavel Ganesan
June 09, 2025
Top10
The RTL coding mistakes that cost the most power and area are the ones that make logic toggle when it does no useful work, or that build more hardware than the function needs. Clocks that run when registers hold their value, glitchy deep logic, oversized buses, resets on every flop and accidental latches are the usual culprits. Synthesis tools recover some of this, but they cannot undo an architecture or coding style that asks for waste. Below a…
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Murugavel Ganesan
April 07, 2025
Top10
The PCIe and CXL questions that come up most in semiconductor interviews cover ten areas: how PCIe evolved to PAM4 and FLIT mode, the three CXL protocols, how CXL shares the PCIe physical layer, coherency, error handling, power states, signal integrity at 64 GT/s and above, the protocol stack, use cases, and link bring-up debug. Interviewers are rarely after a recited specification. They want to see that you can explain why each feature exists, …
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Murugavel Ganesan
March 26, 2025
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