Displaying posts in the categoryAdvanced Packaging
Advanced Packaging articles
Verification
UCIe is often described as a plug-and-play standard for chiplets, and its guiding principles do aim at that. Version 3.0 takes the top data rate to 64 GT/s and the specification now runs from the bump map up to firmware download. Read that as the promise. A team buying a die from another company has a narrower question: which parts of this link will work on first power-up, and which depend on choices nobody has written down yet? This post work…
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Murugavel Ganesan
November 06, 2026
Process Technology
Hybrid bonding joins two pieces of silicon with no solder at all. Flat dielectric meets flat dielectric, copper pads meet copper pads, and an anneal makes the joint permanent. That removes the bump, and with it the floor on how close connections can sit. Research wafers are now bonded at a 200 nm pitch, while shipping server processors use about 9 µm. That gap of roughly forty-five times is the subject of this post. Wafer-to-wafer and die-to-w…
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Murugavel Ganesan
November 05, 2026
Process Technology
For more than fifty years, power and signals have shared the same side of the chip. Backside power delivery ends that. Power comes up through the back of a thinned wafer, and the front metal stack is left mostly to signals. Intel builds this into 18A as PowerVia, and TSMC plans it for A16 as Super Power Rail. The headline benefit is easy to state: less voltage drop and more room for routing. The harder question for a design team is what change…
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Murugavel Ganesan
November 05, 2026
Photonics
For the last two years the hardest thing to get in AI hardware was not the chip itself but the package around it. TSMC's CoWoS capacity has decided how many accelerators can ship. Now TSMC is reported to be weighing another price rise for that packaging, and on 2 November 2026 Marvell agreed to buy Lumentum for about $115 billion to get into optical interconnect. Together they show where the bottleneck is moving: from packaging to the links…
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Murugavel Ganesan
November 03, 2026
Semiconductor Manufacturing
Originally published on LinkedIn . Advanced packaging is now one of the main ways the semiconductor industry improves system performance. As transistor scaling slows and gets more expensive, the gains increasingly come from how dies are split, stacked and connected inside one package. That makes packaging a design decision taken at the start of architecture work, not a step at the end of manufacturing. Packaging is no longer a footnote in sem…
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Murugavel Ganesan
August 27, 2026
Semiconductor Manufacturing
EMIB and CoWoS are the two leading ways to join several chiplets and HBM stacks in one package. Intel's EMIB (Embedded Multi-die Interconnect Bridge) embeds small silicon bridges in an organic substrate only where two dies meet. TSMC's CoWoS (Chip on Wafer on Substrate) places all the dies on a large interposer that carries the wiring between them. In short, EMIB saves silicon and cost and eases warpage, while CoWoS has been the proven …
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Murugavel Ganesan
May 12, 2026
Tutorials
Choosing a BGA package changes far more than the footprint. The package type, ball pitch, body size and thermal design decide how many PCB layers you need, whether the board needs HDI microvias, how tight the assembly window is, how solder joints are inspected and how long they survive thermal cycling. That is why BGA selection should be reviewed by design, PCB fabrication and assembly teams together, not left as a schematic-level decision. Ba…
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The Editor's Desk
May 04, 2026
