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Process Technology articles
Process Technology
Hybrid bonding joins two pieces of silicon with no solder at all. Flat dielectric meets flat dielectric, copper pads meet copper pads, and an anneal makes the joint permanent. That removes the bump, and with it the floor on how close connections can sit. Research wafers are now bonded at a 200 nm pitch, while shipping server processors use about 9 µm. That gap of roughly forty-five times is the subject of this post. Wafer-to-wafer and die-to-w…
by
Murugavel Ganesan
November 05, 2026
Process Technology
For more than fifty years, power and signals have shared the same side of the chip. Backside power delivery ends that. Power comes up through the back of a thinned wafer, and the front metal stack is left mostly to signals. Intel builds this into 18A as PowerVia, and TSMC plans it for A16 as Super Power Rail. The headline benefit is easy to state: less voltage drop and more room for routing. The harder question for a design team is what change…
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Murugavel Ganesan
November 05, 2026
Process Technology
Building an automotive chip on a commercial wafer process and then qualifying it to AEC-Q100 is sometimes the only option, but on mature nodes it is usually a false saving. AEC-Q100 shows that sampled parts survived a set of stress tests; it does not make the silicon as robust as a process built for automotive. What you save on wafers you tend to spend again on screening, yield loss, test time and field reliability risk. In the semiconductor w…
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Murugavel Ganesan
December 12, 2025
Video
Five forces will shape technology through 2026: AI staying mainly in the cloud, the move to new transistor structures, HBM4 leading the memory recovery, advanced packaging and photonics tackling heat and bandwidth, and the US and China rivalry splitting the technology supply chain. None of them is a new gadget or app. They come from the places where compute, manufacturing and geopolitics meet. This is an opinion piece written in November 2025. …
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Murugavel Ganesan
November 10, 2025
Technology
A PDK (Process Design Kit) is the package of models, rules, libraries and verification decks that a foundry supplies for one manufacturing process, so that chip designers can simulate, lay out and check a design before it is built. It is the foundry's process described in a form that EDA tools can read. Every chip that reaches silicon, from a smartphone processor to a power converter, was designed against a PDK, which is why it is often call…
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Murugavel Ganesan
September 16, 2025
Semiconductor Manufacturing
Gallium nitride (GaN) is a wide-bandgap III-V compound semiconductor with a bandgap of about 3.4 eV, three times that of silicon. That wide bandgap gives it a breakdown field roughly ten times higher than silicon, and its AlGaN/GaN heterostructure forms a fast, high-density electron channel without doping. Together these let GaN transistors switch faster, at higher voltage and with lower losses than silicon in chargers, power supplies and RF amp…
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Murugavel Ganesan
July 01, 2025
Tutorials
Gallium arsenide (GaAs) is a III-V compound semiconductor made from gallium and arsenic. It matters because it does two things silicon does poorly: its electrons move about six times faster, which suits radio-frequency amplifiers and switches, and its direct bandgap lets it emit light efficiently, which suits LEDs, lasers and high-efficiency solar cells. Silicon still wins on cost, wafer size and integration density, so GaAs lives in the parts…
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Murugavel Ganesan
June 24, 2025
