Displaying posts in the categoryChiplets
Chiplets articles
Through-Glass Vias
Intel put glass core substrates in the headlines in September 2023 and said complete solutions would reach the market in the second half of this decade. More than three years on, a technical note from the IEEE Electronics Packaging Society, updated in November 2025, still says glass has yet to be commercialised. Both statements can be true, and the gap between them is the subject of this post. Glass solves real problems in large AI packages, b…
by
Murugavel Ganesan
November 12, 2026
Verification
UCIe is often described as a plug-and-play standard for chiplets, and its guiding principles do aim at that. Version 3.0 takes the top data rate to 64 GT/s and the specification now runs from the bump map up to firmware download. Read that as the promise. A team buying a die from another company has a narrower question: which parts of this link will work on first power-up, and which depend on choices nobody has written down yet? This post work…
by
Murugavel Ganesan
November 06, 2026
Process Technology
Hybrid bonding joins two pieces of silicon with no solder at all. Flat dielectric meets flat dielectric, copper pads meet copper pads, and an anneal makes the joint permanent. That removes the bump, and with it the floor on how close connections can sit. Research wafers are now bonded at a 200 nm pitch, while shipping server processors use about 9 µm. That gap of roughly forty-five times is the subject of this post. Wafer-to-wafer and die-to-w…
by
Murugavel Ganesan
November 05, 2026
Semiconductor Manufacturing
Originally published on LinkedIn . Advanced packaging is now one of the main ways the semiconductor industry improves system performance. As transistor scaling slows and gets more expensive, the gains increasingly come from how dies are split, stacked and connected inside one package. That makes packaging a design decision taken at the start of architecture work, not a step at the end of manufacturing. Packaging is no longer a footnote in sem…
by
Murugavel Ganesan
August 27, 2026
Semiconductor Manufacturing
EMIB and CoWoS are the two leading ways to join several chiplets and HBM stacks in one package. Intel's EMIB (Embedded Multi-die Interconnect Bridge) embeds small silicon bridges in an organic substrate only where two dies meet. TSMC's CoWoS (Chip on Wafer on Substrate) places all the dies on a large interposer that carries the wiring between them. In short, EMIB saves silicon and cost and eases warpage, while CoWoS has been the proven …
by
Murugavel Ganesan
May 12, 2026
Semiconductor Industry
A chiplet is a small die designed to be combined with other dies in one package so that together they behave like a single large chip. The idea took off because giant monolithic dies at advanced nodes became too costly to yield, and because not every circuit benefits from the newest process. Better die-to-die interconnect and advanced packaging made it practical, AMD proved it commercially with Zen 2 in 2019, and Intel, Apple and NVIDIA followed…
by
Murugavel Ganesan
April 02, 2026
