Silicon qualification testing is a set of stress tests run on samples of a new chip, package or process to show that it meets the reliability and environmental standards required for its market. Devices are pushed harder than they would be in normal use, with high temperature, voltage, humidity and temperature cycling, so that years of wear show up in weeks. If the samples pass with zero or very few failures, the product is declared qualified and can be released for volume shipment.
Key takeaways
- Qualification is done on samples, usually from several manufacturing lots, not on every chip shipped.
- It uses accelerated stress: heat, voltage, humidity and thermal cycling speed up the failure mechanisms that occur in the field.
- Industry standards define the tests and pass criteria. JEDEC JESD47 is the common baseline, and AEC-Q100 is the reference for automotive ICs.
- Results are turned into failure rates, often in FIT (failures per billion device hours), using acceleration models such as Arrhenius.
- Qualification is repeated, at least in part, when the design, die, package, fab or process changes.
What qualification testing is
Qualification testing is a type of testing performed on silicon chips and integrated circuits to verify that they meet required reliability and environmental standards. During qualification testing, devices are subjected to a series of tests designed to simulate real-world operating conditions, including temperature, voltage and stress conditions.
The purpose of qualification testing is to ensure that devices are suitable for use in their intended applications, and that they can withstand the environmental and operating conditions they will be exposed to in the field. Qualification testing may include tests such as temperature cycling, thermal shock and humidity testing, among others.
It is different from the tests every chip goes through. Wafer sort and final test check that each unit works when it leaves the factory. Qualification asks a different question: will this design, built on this process and in this package, keep working for the lifetime the customer expects?
Where qualification sits in the product flow
- First silicon and characterisation: engineers measure the chip across voltage and temperature to set data sheet limits.
- Qualification plan: the team picks the stress tests, sample sizes and pass criteria from the target standard and the customer's mission profile.
- Stress and read points: units are stressed and electrically tested at set intervals, for example at 168, 500 and 1,000 hours.
- Failure analysis: any failing unit is analysed to find the root cause, and the design or process is fixed if needed.
- Qualification report and release: the results are documented and the product moves to production.
Common qualification tests
| Test | What it stresses | Typical reference |
|---|---|---|
| High temperature operating life (HTOL) | Wear-out of transistors and wiring under bias at high temperature, often around 125 C for about 1,000 hours | JESD22-A108 |
| Early life failure rate (ELFR) | Infant mortality from latent defects, using a short, high-stress run on many units | JESD74 |
| Temperature cycling | Mechanical fatigue in the package, solder and bond wires from repeated hot and cold swings | JESD22-A104 |
| Thermal shock | Fast temperature changes, usually liquid to liquid, harsher than air cycling | JESD22-A106 |
| Temperature humidity bias (THB) and HAST | Corrosion and moisture ingress under voltage; HAST uses pressure to speed this up | JESD22-A101, JESD22-A110 |
| High temperature storage | Material and bond degradation with no bias applied | JESD22-A103 |
| ESD (HBM and CDM) | Robustness to electrostatic discharge during handling | ANSI/ESDA/JEDEC JS-001 and JS-002 |
| Latch-up | Parasitic thyristor triggering by over-current or over-voltage | JESD78 |
Automotive parts follow AEC-Q100, which builds on these JEDEC methods with stricter conditions, temperature grades (for example Grade 1 covers -40 C to +125 C ambient) and extra tests.
A worked example: turning HTOL results into a failure rate
The numbers below are illustrative, but the method is the one used in practice.
Suppose a team runs HTOL on 3 lots of 77 units each, which is a common sample plan in JESD47, giving 231 devices. They run 1,000 hours at a junction temperature of 125 C, and no device fails.
- Device hours at stress: 231 x 1,000 = 231,000 hours.
- Acceleration factor using the Arrhenius model, with an assumed activation energy of 0.7 eV and a use temperature of 55 C: AF = exp[(Ea / k) x (1/Tuse - 1/Tstress)], with k = 8.617 x 10-5 eV/K, Tuse = 328 K and Tstress = 398 K. This gives AF of about 78.
- Equivalent field hours: 231,000 x 78, about 18 million device hours.
- With zero failures, the upper bound on failure rate at 60 percent confidence uses the chi-square value 1.83 for two degrees of freedom: 1.83 / (2 x 18 x 106), about 5 x 10-8 per hour, or roughly 51 FIT.
- At 90 percent confidence (chi-square 4.61) the same data gives roughly 128 FIT.
This shows why sample size and stress temperature matter: a zero-fail result only bounds the failure rate, and a tighter bound needs more units, more hours or more acceleration.
Why it matters
Qualification testing is an important step in bringing silicon chips and integrated circuits to production, as it helps to improve the reliability and performance of the final product by exposing weaknesses before customers see them. By verifying that devices meet required reliability and environmental standards, qualification testing helps to ensure that the devices are suitable for use in a wide range of applications, and it helps to reduce the number of warranty claims and returns from customers.
For car, industrial and medical customers, a qualification report is often a contractual requirement before a part can be designed in.
Common mistakes
- Confusing qualification with production test: qualification proves the design and process, production test screens each unit.
- Using an activation energy that does not match the failure mechanism, which can overstate the acceleration factor.
- Stressing beyond the point where new failure mechanisms appear that would never occur in the field.
- Forgetting to requalify after a change of fab, package supplier, die shrink or bill of materials.
FAQ
How long does chip qualification take?
Often a few months, since HTOL alone runs around 1,000 hours (about six weeks) plus preparation, read points and analysis.
Is every chip qualification tested?
No. Qualification uses samples. Every shipped chip goes through wafer sort and final test instead, and sometimes burn-in.
What is the difference between JEDEC and AEC-Q100 qualification?
JEDEC JESD47 is a general baseline for commercial and industrial parts. AEC-Q100 is the automotive standard with tighter conditions and extra tests.
What does FIT mean?
Failures in time: the number of failures expected in one billion device hours of operation.
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