Through HBM3E, the base die at the bottom of a memory stack was a memory maker's own part, built on its own process and sold inside a standard product. Custom HBM breaks that up. The memory controller can move from the host chip into the base die, a logic foundry makes the die, and a customer may want its own circuits in there as well.
The technical case is well covered. The commercial one is not, because a part that used to have one owner now touches four or five companies. This post sets out the value chain link by link and asks three plain questions of each: who designs it, who pays for it, and who is left holding the loss when it fails. A small worked example shows why the third question matters most.
Key takeaways
- No custom HBM contract terms have been published. What follows on payment and yield is reasoned from public statements, and we mark it as our reading.
- Design has no single owner yet. Memory makers, design houses and possibly the largest customers are all positioning for it, and the arrangement is expected to vary by project.
- Micron says it expects customised HBM4E to carry higher gross margins than the standard part, so customers should expect to pay for customisation.
- Synopsys expects fewer than 20 custom projects a year, which suggests a business for the largest buyers and not a general option.
- Yield is the unsettled link. In our illustrative model, whoever pays for base die test coverage is not the party who saves most from it, so the contract has to deal with that directly.
What is changing in the base die
JEDEC published the HBM4 standard, JESD270-4, in April 2025: up to 8 Gb/s across a 2048-bit interface, up to 2 TB/s per stack, and 32 channels against 16 in HBM3. A standard part lets a buyer treat suppliers as broadly interchangeable. That is what custom HBM gives up in exchange for a tighter fit with one host chip.
The move to logic processes has already happened, even for standard parts. SK hynix said in April 2024 that it would use TSMC's logic process for the HBM4 base die, having used its own technology up to HBM3E, and named customisation as one of the reasons. Samsung announced mass production of HBM4 in February 2026 with a base die on its own 4 nm foundry process. Micron has built its HBM4 base die in-house but says TSMC is expected to make the logic dies for both standard and custom HBM4E.
Custom goes further. TSMC's presentation at its OIP forum in Amsterdam, as reported in December 2025, placed its C-HBM4E base die on N3P at 0.75 V, against 0.8 V for an N12 HBM4 base die and 1.1 V for the older DRAM-process die. Memory controllers move into the base die and the PHY becomes a custom design. TSMC's stated efficiency gains were about 1.5 times for N12 and 2 times for N3P. These are vendor figures.
The payoff for the host chip is the main selling point. Marvell's December 2024 announcement claimed up to 70% lower interface power and up to 25% die area savings that can be spent on compute, along with up to 33% more HBM stacks per accelerator. These are also vendor claims, and we found no independent measurements.
The value chain, link by link
The "who does the work" column follows public descriptions. The last two columns are our reading, reasoned from the statements in the rest of this post, since none of the companies has published how it splits these costs.
| Link | Who does the work | Who probably pays | Who probably carries a failure here |
|---|---|---|---|
| Requirements | The hyperscaler or GPU company, which knows its workload and host architecture | The customer, in its own engineering budget | The customer, if the wrong functions are moved and the design misses its window |
| Base die logic design | Varies: the customer, a design house such as Marvell, or the memory maker's custom team | The customer, directly as a design fee or indirectly in the stack price | The design owner for bugs, with the schedule cost falling on the customer |
| Interface IP | IP vendors for controller and die-to-die PHY. Synopsys says the memory maker supplies the TSV PHY that connects to the stack | Whoever holds the design contract | The design owner, with the memory maker answerable for its own TSV block |
| Base die wafers | A logic foundry: TSMC for SK hynix and, for HBM4E, Micron. Samsung uses its own | The party that places the wafer order, which may vary by project | The wafer buyer for defective dies, unless known good dies are bought |
| DRAM core dies | The memory maker | Included in the stack price | The memory maker |
| Stacking and stack test | The memory maker on standard parts. On custom, agreed per project, perhaps with a separate assembly house | Included in the stack price | The assembler for its own process damage. A base die escape caught here is the contested case |
| Package integration | The chip's integrator and its packaging partner, typically on a silicon interposer | The customer | The customer, subject to whatever warranty the stack carries |
Who designs
Three models are visible. The names are ours.
- Memory maker led. The customer specifies and the memory maker delivers a finished stack. SK hynix America runs an HBM architect design team in San Jose working with US customers on base dies, according to NewsPim as cited by TrendForce. The Elec reported in January 2026 that Samsung runs separate standard and custom HBM teams and added 250 engineers for custom projects. Micron describes customisation as an option on its HBM4E.
- Design house led. A custom silicon company works with the hyperscaler and the memory makers. Marvell named Micron, Samsung and SK hynix as collaborators in December 2024.
- Customer owned. The buyer designs its own die and has it fabricated. Commercial Times reported in August 2025 that Nvidia had started developing its own base die on a 3 nm node, with small trial production in the second half of 2027. This is a market rumour, not an Nvidia statement.
These may not be stable categories. In a Semiconductor Engineering article of 20 August 2026, Bryon Moyer says design is likely to fall to the consuming company or a design house, and cites an SK hynix presentation describing memory makers as short of design resources. Marvell's Khurram Malik describes several engagement models in the same piece. The custom teams at Samsung and SK hynix point the other way, so the split is still being contested.
Who pays
Three pieces of evidence bear on the money, and none gives a price.
- Customers are expected to pay a premium. Micron said in September 2025 that customised offerings should deliver higher gross margins. In May 2026 its EVP Manish Bhatia said customers were expected to be willing to pay for customisation.
- The die itself costs more. Herald Business estimated in August 2026 that TSMC HBM4 base dies could cost 3 to 4 times as much as SK hynix's 1b core dies, with the gap expected to widen on HBM4E. It also reported that long-term agreements make these costs hard to pass on. This is a press estimate, and SK hynix said "some of the reports are not true" without saying which parts.
- Volume decides who can play. Synopsys's Rob Kruger called these projects a big lift that needs significant volume, and Synopsys expects fewer than 20 a year. The Asia Business Daily noted in February 2026 that a cancelled order can leave a custom product hard to sell, which is a risk standard parts do not carry in the same way.
A quick illustration of the volume point, using an assumed development cost of $40 million. Over 1,000,000 stacks that is $40 a stack, or $320 on a package with eight stacks. Over 200,000 stacks it is $200 a stack, or $1,600 a package. The second figure has to be earned back from host area and power, which is a much harder claim to defend.
A worked example: who bears a bad base die
Semiconductor Engineering's 12 May 2026 article by Anne Meixner explains the stakes. The base die is the only access path to the memory above it. HBM accounts for nearly half the cost of AI chips, at a time when supply is tight, as we set out in The AI Memory Squeeze, and Aehr Test's Vernon Rodgers points out that a bad base die can mean 16 DRAM dies thrown away. Teradyne's Hanh Lai says integrators such as Nvidia and AMD worry about final package yield, while memory makers prioritise low-cost test.
Here is that tension in numbers. Every figure below is an illustrative assumption, not data from any supplier.
| Where a bad base die is caught | What is lost | Cost |
|---|---|---|
| Wafer sort | The base die | $60 |
| Stack test | Base die $60, 12 core dies at $20 each ($240), assembly and test $50 | $350 |
| After package assembly, no rework | 8 stacks at $350 ($2,800), host silicon $4,000, interposer and package $1,000 | $7,800 |
Take 1,000 base dies with 2% defective, so 20 bad ones. Stack test catches 95% of what reaches it. Compare two levels of wafer sort coverage:
| 90% sort coverage | 99% sort coverage | |
|---|---|---|
| Caught at sort | 18 dies, $1,080 | 19.8 dies, $1,188 |
| Caught at stack test | 1.9 dies, $665 | 0.19 dies, $66.50 |
| Reach the package | 0.1 dies, $780 | 0.01 dies, $78 |
| Total loss | $2,525 | $1,332.50 |
| Share at sort / stack / package | 43% / 26% / 31% | 89% / 5% / 6% |
Better coverage saves $1,192.50 per 1,000 dies, or about $1.19 a die, before counting the extra test cost. Now look at who gains. The sort-level loss goes up by $108. The stack owner saves $598.50 and the integrator saves $702. So a base die owner who carries only its own scrap, and also pays for the extra test, is worse off for doing the right thing.
That is the main commercial problem with custom HBM. Through HBM3E, a memory maker typically owned the base die, the stack and the test programme, so these trade-offs stayed inside one company. Split the die from the stack and someone has to write the incentive down.
Who owns yield: a practical split
Neither Semiconductor Engineering article assigns yield ownership, and we found no public source that does. Meixner reports that a 12-high stack can see 3 to 12 test insertions, depending on quality targets. Each insertion is a natural handover point. Our suggestion is to agree the following before design starts:
- Define the known good die at each handover. State the test coverage and the test program version that the base die must pass before it goes to stacking, and who owns that program.
- Split test escapes by evidence. A die that passed sort and failed at stack test needs a failure analysis route and an agreed rule on who pays for the lost DRAM.
- Share the data. Sort, stack and package results sit with different companies. Without shared lot-level data, nobody can tell a design margin problem from a process one.
- Agree the field path. Synopsys's Faisal Goriawalla cites hyperscaler data putting HBM failures as the top cause of GPU failures in data centres. If a stack fails in service, decide who investigates a die that one company designed, another made and a third assembled.
A decision tool for buyers
Answer these before committing to a custom base die:
- Is the volume there? Divide your full development cost by committed stack volume, and compare it with the host area and power you can actually claim back.
- Do you need a second source? With the TSV PHY coming from the memory maker, we would expect a custom die to need rework for each DRAM supplier. Ask for this to be costed.
- Which foundry risk are you taking? Base dies now compete for logic capacity. Hankyung reported in March 2026 that Samsung would give over half of its Pyeongtaek foundry capacity to its own HBM4 base dies.
- Does the schedule work? Samsung said in February 2026 that it plans custom HBM samples in 2027. Micron says its first HBM4E will follow the JEDEC standard, with a 2027 ramp. Moyer expects custom stacks in data centres in a year or maybe two. Packaging has to be on the same schedule, and our advanced packaging overview covers what that involves.
If several of these answers are weak, standard HBM4E is the sensible choice, with custom left for a later generation. Our chiplet lifecycle on The Semiconductor Hub shows where supplier and integration decisions like these fall in a programme.
FAQ
Is custom HBM still a JEDEC part?
The DRAM may be close to the standard, but the host-side interface need not be. Marvell's interface and TSMC's custom PHY both depart from the standard one. Check what your supplier means by "custom", because it can range from extra logic to a wholly different interface.
Which node will custom base dies use?
Reports point to 3 nm for premium designs at TSMC, with 12 nm for mainstream server parts at SK hynix. Samsung reports conflict: one from January 2026 mentions 2 nm for custom HBM, while one from March 2026 places HBM4E on 4 nm and 2 nm on HBM5. SK hynix itself says only that it is using the best technology for customer requirements.
Sources
- JEDEC, JESD270-4 HBM4 release, April 2025, as reported by TrendForce, "JEDEC Finalizes HBM4 Standard", 21 April 2025.
- SK hynix, "SK hynix Partners with TSMC to Strengthen HBM Technological Leadership", 19 April 2024.
- Samsung HBM4 announcement of 12 February 2026, as reported by The Korea Times, 12 February 2026.
- Marvell, custom HBM compute architecture announcement, 10 December 2024, as carried by EE Times Asia.
- TrendForce News: on TSMC C-HBM4E, 1 December 2025; on Micron HBM4E and margins, 24 September 2025; on Micron and TSMC logic dies, 22 May 2026; on Nvidia's base die (citing Commercial Times), 18 August 2025; on Samsung custom HBM4E (citing The Elec, ZDNet), 23 January 2026; on SK hynix and TSMC 3 nm (citing Chosun Daily, ETNews), 20 March 2026; on Samsung Pyeongtaek capacity (citing Hankyung), 20 March 2026; on SK hynix and Intel (citing Herald Business, NewsPim), 31 August 2026.
- Bryon Moyer, "How Will The Custom HBM Business Work?", Semiconductor Engineering, 20 August 2026.
- Anne Meixner, "HBM Shifts Testing Left To Preserve AI Chip Yield", Semiconductor Engineering, 12 May 2026.
- The Asia Business Daily: on custom HBM at Semicon Korea, 16 February 2026; on SK hynix's Q1 2026 call, 23 April 2026.
The worked example and the $40 million development cost are illustrative. Vendor figures are the companies' own claims and targets, and many items here are press reports the companies have not confirmed. The commercial suggestions are prompts for discussion and are not legal advice.
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