Hybrid Bonding From First Principles: Pitch, Yield and Who Is Ready

Hybrid bonding joins two pieces of silicon with no solder at all. Flat dielectric meets flat dielectric, copper pads meet copper pads, and an anneal makes the joint permanent. That removes the bump, and with it the floor on how close connections can sit. Research wafers are now bonded at a 200 nm pitch, while shipping server processors use about 9 µm.

That gap of roughly forty-five times is the subject of this post. Wafer-to-wafer and die-to-wafer bonding sit at very different points on the pitch scale, and they fail for different reasons. Below we build the argument from the basics, run a small model you can redo with your own numbers, and set out who is ready for what.

Key takeaways

• Pitch sets the overlay budget. imec's rule of thumb is overlay of about one fourth of the pitch, so each halving of pitch halves the alignment budget and quadruples the pad count.
• Wafer-to-wafer leads on pitch: imec reported 400 nm at IEDM 2023, and imec and EV Group have since claimed 200 nm. Its weakness is that it cannot avoid pairing good dies with bad ones.
• Die-to-wafer stacks only known-good dies and allows unequal die sizes. imec's published result was 2 µm in 2024, with 1 µm as its stated goal.
• The choice comes down to a simple break-even: die-to-wafer wins while its bond yield stays above incoming die yield multiplied by the wafer-to-wafer bond yield.
• Memory is the caution. Reporting from 2026 says SK hynix and Samsung are holding hybrid bonding back in HBM, partly because a relaxed height limit took away the urgency.

The bond, from the basics

imec describes the classical wafer flow in a few steps. Cavities are etched into a bonding dielectric, then filled with barrier, seed and copper. Chemical-mechanical polishing leaves a flat dielectric with the copper sitting a few nanometres below it. The wafers are aligned and touched at the centre at room temperature, and a bonding wave closes the gap out to the edge. A later anneal forms the permanent dielectric and copper bonds.

The YAP+ yield model by Chen and Gupta at UCLA, a preprint under review, treats overall yield as the product of three terms:

• Overlay. Pads land too far from their partners.
• Copper recess. Too much recess and the copper does not close the gap when it expands. Too little and it pushes the dielectric apart.
• Particles. A particle props the surfaces open and leaves a void.

These terms respond differently to pitch. The model finds that overlay and recess get harder as pitch shrinks, because tolerances tighten and pad counts rise. Defect yield stays largely unaffected by pitch, because voids are larger than the pitch anyway. A particle hurts at every pitch, while overlay starts to hurt at a particular pitch.

What each pitch asks for

A full grid of pads gives (1000 / pitch in µm) squared per mm², and imec's rule gives the overlay budget.

Pitch	Pads per mm²	Pads on 100 mm²	Overlay at pitch / 4	Where it stands
9 µm	12,346	1.2 million	2.25 µm	Intel's first-generation Foveros Direct figure
6 µm	27,778	2.8 million	1.5 µm	TSMC SoIC today, as reported after its 2026 symposium
3 µm	111,111	11 million	750 nm	Intel's stated second generation, no date given
2 µm	250,000	25 million	500 nm	imec die-to-wafer research, 2024
1 µm	1,000,000	100 million	250 nm	Industrial wafer-to-wafer, per imec. Die-to-wafer research target
400 nm	6,250,000	625 million	100 nm	imec wafer-to-wafer, IEDM 2023
200 nm	25,000,000	2.5 billion	50 nm	imec and EV Group wafer-to-wafer claim, 2026

The published overlay results fit the rule. imec's die-to-wafer work reported below 350 nm at 2 µm, which is 17.5% of pitch. The imec and EV Group result reported below 40 nm at 200 nm, or 20% of pitch.

The pad count shows why nobody treats each pad as an independent coin toss. Suppose every pad must work and you want 99% interconnect yield on a 100 mm² die. Then each pad may fail about once in 123 million at 9 µm, and once in 62 billion at 400 nm. Real layouts avoid this, because not every pad need be critical. YAP+ finds that fewer critical pads raise yield, and it suggests redundancy as a practical mitigation.

A worked model: where the crossover falls

Every number in this section is an illustrative assumption, not data from any foundry or tool maker. Replace them with your own.

Assumption	Wafer-to-wafer	Die-to-wafer
Gross dies per wafer, same on top and bottom	600	600
Die shift in x and in y, 1 sigma	20 nm	75 nm
Bond yield from all causes other than overlay	98%	95%
Failure limit on die shift	pitch / 4	pitch / 4
Test before bonding	None usable, wafers are paired blind	Perfect sort of top dies and bottom sites

Step 1: bond yield against pitch. Take x and y shifts as independent normal distributions, and require both to stay inside the limit. Overlay yield is then the probability for one axis, squared, and bond yield is that figure multiplied by the non-overlay term. At 500 nm pitch on die-to-wafer, the limit is 125 nm, which is 1.667 sigma. One axis passes 90.4% of the time, squared gives 81.8%, and multiplying by 95% gives 77.7%.

Step 2: good stacks from one pair of wafers. With die yield Y on both wafers and bond yields B:

• Wafer-to-wafer: 600 × Y × Y × B. Good and bad dies pair up by position, so yield is squared.
• Die-to-wafer: 600 × Y × B. Good dies go onto good sites only.

At 70% die yield and 1 µm pitch, that gives 600 × 0.7 × 0.7 × 0.98 = 288 for wafer-to-wafer, against 600 × 0.7 × 0.948 = 398 for die-to-wafer.

Pitch	D2W bond yield	W2W bond yield	70% dies: W2W stacks	70% dies: D2W stacks	95% dies: W2W stacks	95% dies: D2W stacks
2 µm	95.0%	98.0%	288	399	531	542
1 µm	94.8%	98.0%	288	398	531	541
700 nm	91.3%	98.0%	288	383	531	520
500 nm	77.7%	98.0%	288	326	531	443
400 nm	63.5%	98.0%	288	267	531	362

Setting the two formulas equal gives the one line worth remembering: die-to-wafer wins while its bond yield stays above Y multiplied by the wafer-to-wafer bond yield. At 70% die yield the bar is 68.6%, and the crossover falls between 500 nm and 400 nm. At 95% the bar is 93.1%, and the crossover moves out to between 1 µm and 700 nm. Good incoming dies shrink the value of sorting, so the better your dies, the coarser the pitch at which wafer-to-wafer takes over.

Placement accuracy matters just as much. Cut the die-to-wafer sigma from 75 nm to 40 nm, and at 400 nm its bond yield rises to 92.7%. That gives 389 stacks against 288 at 70% die yield, and 528 against 531 at 95%, which is a near tie.

The model leaves out rotation, magnification, test escapes and cost. Holding wafer-to-wafer at a flat 98% is also generous, since YAP+ finds recess yield falling at fine pitch on larger chiplets. Tool time is easy to estimate, though. At Besi's listed 2,000 cycles per hour, a dry-cycle best case, placing 420 dies takes about 12.6 minutes per wafer.

Why the two routes stall in different places

Wafer-to-wafer is limited by distortion. imec says wafers deform during bonding, that simulations suggest the bonding wave does not travel uniformly, and that the overlay needed at 250 nm across a full 300 mm wafer calls for next-generation equipment. At 300 nm it used lithography corrections before bonding to reach below 25 nm on 95% of dies. EV Group's September 2026 release claims below 40 nm on 100% of dies at 200 nm on its GEMINI FB, and calls the process high yielding. That release gives no yield number.

Die-to-wafer is limited by the die's journey. A wafer goes from polish to bond in a controlled state, while a die has to survive thinning, singulation and pick-and-place with its surface intact, a challenge imec's Anne Jourdain set out at the 2025 IEEE Hybrid Bonding Symposium. imec used plasma dicing to avoid particles and damage, and held copper recess below 2.5 nm. Its 2024 result was Kelvin electrical yield above 85% and daisy-chain yield above 70%. Those are research test structures, so they do not predict product yield.

YAP+ also finds that die-to-wafer loses more yield going from 1 µm to 300 nm, especially on larger chiplets.

Who is ready for what

Area	Status as published	How firm
Image sensors	Sony used hybrid bonding in mass-produced sensors in 2016	Journal review, 2025
3D NAND	Kioxia builds CMOS and cell array on separate wafers and bonds them in its 218-layer generation 8 device	Company technical note
Intel logic	Clearwater Forest stacks 12 compute tiles on 3 base tiles using Foveros Direct 3D at 9 µm. Intel said in October 2025 it would ship in the first half of 2026. Intel 18A-PT is stated at below 5 µm	Intel statements, 9 µm via press coverage of its briefing
TSMC logic	A14-to-A14 SoIC for production in 2029, with 1.8 times the die-to-die I/O density of N2-on-N2. Pitch reported as 6 µm today and 4.5 µm by 2029	Density and date from TSMC, pitch from press reports
SK hynix HBM	Microbumps continue through HBM4E, and hybrid bonding is in development for stacks of 20 or more	Press accounts of a Hot Chips 2026 talk
Samsung HBM	Reportedly planning about 50 die-to-wafer bonders, with large-scale production around 2029 to 2030	Unconfirmed, TrendForce citing Korean press
Die-to-wafer tools	Applied and Besi's Kinex is claimed as the first integrated system, in use at several customers. Besi lists 100 nm at 3 sigma, and NHanced cites 200 nm and pitches down to 1 µm	Vendor claims

TSMC's two figures agree with each other: (6 / 4.5) squared is 1.78, close to the stated 1.8, if N2-on-N2 sits near 6 µm. That is our inference, and TSMC has not said so. Also compare Besi's 100 nm with NHanced's 200 nm on what appears to be the same machine family. Besi qualifies its figure as "worst corner GOG", which we read as a glass-on-glass test. A tool specification and post-bond overlay on product are different numbers, so ask for the second.

Demand does look real. TrendForce reported in October 2026 that Besi's hybrid bonding customers reached 23, with cumulative demand above 215 systems.

Pitch is not HBM's main reason for adopting the technology. ServeTheHome's account of SK hynix's talk puts the pitch gain at below 18 µm, far from the limits above, and lists stack height and heat among the benefits. When JEDEC raised the limit from 720 µm to 775 µm, as reported, the pressure eased.

Repeated bonds are also punishing. On an illustrative 16-high stack with a base die, there are 16 bonds. At 99% each the stack yields 85.1%, and at 97% only 61.4%. A 90% stack needs about 99.34% per bond. Herald Business reports an SK hynix America senior director calling 90 to 98% yield a non-negotiable standard before production. The report does not say whether that is per bond or per stack.

Choosing a route

Work through these in order.

1. Are the dies different sizes? If so, use die-to-wafer. Wafer pairing needs matching grids, and imec lists unequal sizes among die-to-wafer's advantages.
2. Do you need finer than about 1 µm? Then wafer-to-wafer is the only route with published results there that we could find. Treat finer die-to-wafer as a bet on research.
3. Do you need hybrid bonding at all? imec's Eric Beyne expected solder to stagnate at a 10 to 5 µm pitch. If your link budget closes above that and heat is not the limit, compare bumps first.
4. What is your incoming die yield? Run the break-even above. Large, low-yield compute dies favour sorting, and high-yield dies with a repeating layout favour wafers.
5. Can you sort properly? The die-to-wafer case rests on known-good dies. Check that your test coverage is real, and that probing does not spoil the bonding surface.
6. Can you budget the tool time? Use placements per wafer and a rate measured with your own die handling.
7. How many tiers? Apply the bond yield once per tier, and get a per-bond figure from your supplier.

In short, matched grids with strong die yield lean to wafers, and mixed chiplets at several microns lean to dies. Our chiplet lifecycle on The Semiconductor Hub shows where these packaging decisions fall in a programme.

FAQ

Does a tighter pitch make particles worse?

Not much, according to YAP+, because voids already exceed the pitch. Its authors find that cutting particle density tenfold, to 0.01 per cm², gives about 99% defect yield on both routes at their assumed settings.

Is wafer-to-wafer always better aligned?

The published record favours it so far, though YAP+ assumes similar overlay accuracy for both and still finds a gap. In its model a bad die-to-wafer placement is discarded, while a wafer-to-wafer die near the centre can survive an error at the wafer edge.

Sources

• imec, "Imec demonstrates die-to-wafer hybrid bonding with a Cu interconnect pad pitch of 2µm", press release, 29 May 2024.
• imec, "A path to high-density front and backside wafer connectivity", 19 August 2025.
• A. Jourdain (imec), "Deep Pitch Scaling of Wafer-to-wafer and Die-to-wafer Cu/SiCN Hybrid Bonding", First IEEE Hybrid Bonding Symposium, IEEE.tv, 16 January 2025.
• Z. Chen and P. Gupta, "YAP+: Pad-Layout-Aware Yield Modeling and Simulation for Hybrid Bonding", arXiv:2511.05506, October 2025 (preprint).
• EV Group, press release on hybrid bonding at SEMICON West 2026, 29 September 2026.
• TSMC, press release on the 2026 North America Technology Symposium, 23 April 2026.
• B. T. Williams, "TSMC SoIC roadmap targets 2029 chip stacking", eeNews Europe, 29 April 2026.
• Intel, "Intel Foundry Gathers Customers and Partners, Outlines Priorities", 29 April 2025.
• Intel Foundry, "Cutting-Edge Process Technologies for Data Center", web page, undated.
• K. Kasahara, PC Watch, report on Intel's Clearwater Forest briefing, 9 October 2025.
• Applied Materials, "Applied Materials Unveils Next-Gen Chipmaking Products to Supercharge AI Performance", 7 October 2025.
• Besi, Datacon 8800 CHAMEO ultra plus AC product page, accessed November 2026.
• NHanced Semiconductors, press release, 16 December 2025.
• Kioxia, technical note on CMOS directly Bonded to Array technology, 14 March 2024.
• Bao et al., "Emerging Copper-to-Copper Bonding Techniques", Nanomaterials 15(10):729, 12 May 2025.
• P. Kennedy, "SK hynix HBM Packaging at Hot Chips 2026", ServeTheHome, 23 August 2026.
• P. van Gerven, "Besi faces longer wait as SK Hynix pushes hybrid bonding to HBM5", Bits&Chips, 26 August 2026.
• Kim Hyun-il, Herald Business, report on SK hynix and hybrid bonding yield, 20 September 2026.
• TrendForce News, reports dated 7 July 2026 and 22 July 2026 on HBM timing and Samsung's line, and 27 October 2026 on Applied and Besi.

The worked model uses illustrative numbers. Vendor figures are the companies' own claims and targets, and press reports are labelled as such, as published on the dates shown.