Silicon sort testing, also called wafer sort, wafer probe or circuit probe, is the electrical test of every die on a finished wafer before the wafer is diced into individual chips. A probe card touches the pads of each die, a tester runs a test program, and each die is given a pass or fail bin that is recorded in a wafer map. Only the good dies go on to packaging, which saves the cost of packaging and final-testing parts that were already defective.
Key takeaways
- Sort tests individual dies on the wafer, not just whole wafers, and records the result for each die in a wafer map.
- Its main purpose is to stop bad dies from being packaged, which improves yield at final test and lowers cost.
- Typical tests are continuity (opens and shorts), leakage and supply current, structural scan and memory tests, and key parametric measurements.
- Whole-wafer acceptance is a separate step, wafer acceptance test (WAT), which measures test structures in the scribe lines.
- Sort data feeds yield learning in the fab, and for chiplets it is the first step towards known good die.
What silicon sort testing does
Silicon sort testing is performed while the dies are still on the wafer, before the wafers are diced into individual chips. The purpose is to identify and eliminate defective dies before they are processed further, which helps to improve the yield and quality of the final product.
During sort, the dies are subjected to a series of electrical tests to identify defects, such as shorts or opens, and to measure key electrical parameters, such as resistance, capacitance and leakage current. The results are used to sort the dies into different bins based on their quality and electrical characteristics.
A correction to the first version of this post: it said sort identifies defective wafers and that the highest-quality wafers become high-performance chips. In standard practice, sort bins each die, not each wafer. Whole wafers can be scrapped, but that decision usually comes from wafer acceptance test or from very low sort yield. Speed or performance binning is also done per die, at sort, at final test or both, so dies from the same wafer can end up in different product grades.
How wafer sort works
- Load and align: a wafer prober loads the wafer onto a chuck and aligns it optically to the probe card.
- Touchdown: the probe card's needles or MEMS probes contact the pads or bumps of one or more dies at once. Testing several dies per touchdown is called multi-site testing.
- Run the test program: automatic test equipment (ATE) applies power and signals and measures the responses.
- Bin and map: each die gets a hardware and software bin, stored in an electronic wafer map. Older flows marked bad dies with an ink dot; most fabs now use the map alone.
- Step: the prober moves to the next die or group of dies until the wafer is done.
Typical sort tests
| Test | What it checks |
|---|---|
| Continuity (opens and shorts) | That every pad connects correctly and nothing is shorted to supply or ground |
| Supply current and IDDQ | Quiescent current that is too high often signals a defect |
| Leakage | Input and output leakage at the pins |
| Scan (ATPG) patterns | Stuck-at and transition faults in the logic |
| Memory BIST and repair | Faulty memory cells, with redundant rows or columns fused in to repair them |
| Parametric and trimming | Analogue values such as reference voltages, often trimmed with fuses at this stage |
| Functional or at-speed tests | Limited, because probe contact and tester time make full-speed testing hard on the wafer |
Sort versus WAT versus final test
| Step | What is tested | Main purpose |
|---|---|---|
| Wafer acceptance test (WAT) | Test structures in the scribe lines | Confirm the process stayed in its limits; may reject a whole wafer |
| Wafer sort | Every die on the wafer | Find bad dies before packaging |
| Final test | Every packaged part | Confirm the packaged part meets the data sheet, often at temperature and full speed |
A worked example: why sort pays for itself
These numbers are illustrative.
- A 300 mm wafer with a 100 mm2 die. A common approximation for gross dies per wafer is pi x (d/2)2 / A - pi x d / sqrt(2A), which gives about 707 - 67, or about 640 dies.
- With a defect density of 0.1 per cm2 and the simple Poisson yield model Y = exp(-D x A), yield is exp(-0.1 x 1) = about 90 percent, so roughly 579 good dies and 61 bad ones.
- If packaging and final test cost $3 per unit, skipping the 61 bad dies saves about $183 per wafer.
- If sort costs, say, $100 per wafer in tester and probe card time, it pays for itself, and the saving grows with more expensive packages. For a chiplet going into a costly multi-die package, one bad die can scrap the whole assembly, so sort coverage matters even more.
Why it matters
Silicon sort testing is a critical step in the manufacturing process of silicon chips and integrated circuits, as it helps to identify and eliminate defective dies before they are processed further. By improving the yield and quality of the final product, sort testing helps to reduce the cost of production and improve customer satisfaction.
Sort results also feed back to the fab. Patterns on the wafer map, such as a ring of failures at the edge or a cluster in one area, point engineers towards specific process or equipment problems.
Common mistakes
- Thinking sort and final test are the same. Sort cannot easily test at full speed or at all temperatures, so some defects only appear after packaging.
- Ignoring probe damage. Repeated touchdowns can damage pads and cause bonding problems later.
- Treating every failing die as random. Wafer map patterns often reveal a systematic cause.
FAQ
Is wafer sort the same as wafer probe?
Yes. Wafer sort, wafer probe, circuit probe and electrical die sort are different names for the same step.
What is a wafer map?
A file that records the bin of every die by its position on the wafer, used to pick good dies at assembly and to analyse yield.
What is known good die?
A die tested well enough at wafer level to be trusted in a multi-die package without being tested again on its own, important for chiplets and stacked memory.
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