CFET Explained: What Stacking nFET on pFET Really Costs

Put the nFET directly on top of the pFET and the two no longer need separate floor space. On paper that halves a logic cell. An Intel engineer told IEEE Spectrum in 2023 that an inverter at maximum scaling would be 50 percent of the size of an ordinary CMOS one. Complementary FET, or CFET, is now the expected successor to nanosheets, and imec places its first use at the A7 node.

The published cell heights tell a more modest story than that 50 percent. Imec talks about 4.5 tracks and below for first CFET, against 5.5 tracks for nanosheets at A10. So where does the rest go? This post follows one small logic cell through height, contacts and self-heating, and keeps a running account of the area, with a worked example you can redo using your own numbers.

Key takeaways

• Stacking removes the n-to-p separation from the cell height. It does not remove the power rails, the signal tracks or the vertical connections, and those set the height you actually get.
• Imec's published path runs from 4T single-row cells to 3.5T double-row cells, and on to 3T for A3 and A2. These are research and roadmap figures, and no foundry has announced a CFET production node in any source we read.
• The bottom device is the hard one to contact. Imec reported access resistance falling from 1753 to 378 Ωµm with a new backside module in 2026, which shows how far the earlier scheme had to come.
• Simulations agree that heat escapes a stack less easily, but how much that matters depends on the conditions. One study shows a far hotter CFET under steady bias and a slightly cooler one in a switching inverter.
• In our illustrative example, a 50% paper saving ends up near 12% at block level.

Where the industry has got to

CFET has moved from single devices to working inverters at gate pitches close to what production needs. The reported points below come from different flows, so they show progress rather than a ranking.

Group and meeting	Reported demonstration	Worth noting
Intel, IEDM 2023	Inverter at 60 nm contacted gate pitch	Bottom device contacted from beneath the silicon
imec, VLSI 2024	Functional devices at 60 nm gate pitch with stacked contacts	18 nm gate length, 50 nm n-to-p vertical separation
TSMC, IEDM 2024	Inverter at 48 nm gate pitch, characterised up to 1.2 V	eeNews Europe reported it as unlikely to enter manufacturing at contemporary nodes
Samsung, VLSI 2026	Stacked FETs at 42 nm gate pitch with three nanosheets per device	As described in the symposium's advance tipsheet
Intel, VLSI 2026	Inverters at 45 nm gate pitch with PowerVia and direct backside contacts	Paper title as listed in the tipsheet

On timing, imec's February 2026 update expects monolithic CFET at A7, taking over from the outer wall forksheet that carries gate-all-around nanosheets to A10. Treat that as a research institute's roadmap and not a product schedule.

Our cell, and the account we will keep

Take a small two-input NAND. To isolate the effect of the architecture, we hold the pitches fixed and change only the stack. Every number here is an illustrative assumption, not foundry data. The track counts borrow from imec's published roadmap, but the pitches, utilisation and upsizing are ours.

Assumption	Value
Cell width	3 gate pitches at 42 nm, so 126 nm
Track pitch	24 nm
Nanosheet cell height	5.5T, so 132 nm
Nanosheet block utilisation	75%
CFET block utilisation	65%
Extra CFET drive needed to hold timing	5% average upsizing

The nanosheet cell occupies 126 × 132 = 16,632 nm². That is our reference. A perfect stack would halve the height to 2.75T and the area to 8,316 nm², matching the 50 percent quoted at the top.

First stop: cell height

Stacking takes the n-to-p space out of the height calculation, as imec put it in 2023. What remains is everything else a cell needs vertically: signal tracks to reach the pins, and room for the power connections and the links between tiers.

The tall via is the clearest cost. In a single-row CFET, the buried device has to reach the wiring above, so a connection runs past the upper device. A DTCO study by Choi et al. (2024) points out that the space between channel and tall via limits channel width. A 2025 Flip FET study by Lu et al. notes that CFET bottom logic must be partly routed on the frontside through such supervias, and credits their removal with half a track of height.

Imec's double-row layout attacks the same problem from another angle. Two rows of stacked devices share a signal wall between them, one for every 3.7 FETs by its study, which also removes the extra high-aspect-ratio via. Imec reported cell height moving from 4T to 3.5T, with SRAM 15% smaller than single-row CFET. The architectures differ, but our reading is that both studies price the tall connection at around half a track.

For our cell, take a 4T single-row result: 126 × 96 = 12,096 nm², or 27.3% below nanosheet. Going from 2.75T to 4T has already spent 22.7 points of the original 50. A 3.5T double-row cell would give 10,584 nm², or 36.4%, which is why that layout matters so much.

One cell type pays far more. A stack with a common gate suits most simple logic. Imec says common-gate devices cover roughly 90% to 95% of basic gates, but flip-flops and multiplexers need the n and p gates driven separately. Lu et al. show a clocked inverter stage taking one more gate pitch on CFET for this reason. Apply that to our cell and the width becomes 168 nm, for 16,128 nm². The saving is down to 3.0%. Your library's real area gain depends on how much of the block is sequential.

Second stop: contacts and pin access

An inverter needs its two drains joined as the output, its gates joined as the input, and each source taken to its own supply. In a stack, those connections have to be built and isolated deep between two tall gates, and the lower device is the difficult one.

Imec's work shows the trade clearly. When it first patterned top and bottom contacts from the front, it found harm to bottom contact resistance and a narrower process window for the top device's source and drain. Moving the bottom contact to the wafer back raised top device survival from 11% to 79% in its VLSI 2024 work, at the price of wafer bonding and thinning.

The backside route then brought its own problems. Imec's September 2026 article describes variable bottom source and drain volume, because the epitaxy seeds from both channel and substrate, and SiGe taking space the contact metal could use. Adding a frontside-formed dielectric isolation layer under the source and drain, plus backside process work, took bottom pFET access resistance from 1753 to 378 Ωµm, a 78% cut by our arithmetic. Drive current rose about fivefold and survival yield went from 45% to 85%.

Parasitics follow the same geometry. A TCAD study by Shahin et al. (2026) names deep metal vias from the power rails and upper interconnect as the largest parasitic resistances. Its 2-tier inverter goes from 0.91 ps without interconnect parasitics to 1.45 ps with them.

Then there is pin access. Imec says aggressive cell scaling limits access to input and output pins, and proposes raising the ratio of gate pitch to metal 1 pitch from about 1:1 to 2:1 at A7. That needs tighter metal 1, which points to advanced lithography such as single-patterned High NA EUV. So some of the area saving reappears as lithography cost, and any shortfall in routability appears as lower utilisation.

In our account, that is the drop from 75% to 65% utilisation. Block area per nanosheet cell is 16,632 ÷ 0.75 = 22,176 nm². Per CFET cell it is 12,096 ÷ 0.65 = 18,609 nm². The saving falls to 16.1%, so routing has taken another 11.2 points.

Third stop: self-heating

A channel wrapped in a low-conductivity gate stack was already poor at losing heat. Stacking adds distance from the substrate for the upper device and places a second heat source next to it. These results are worth reading together, because they do not say quite the same thing.

Study	Conditions	Result
Miao et al. (2025)	Simulated device with NFET on, A14 nanosheet against A7 CFET, ideal heat sink	Peak 433 K for nanosheet, 534 K for CFET. Thermal crosstalk 17% against 32%
Miao et al. (2025)	Simulated switching inverter, 20 fF load	CFET rises 68.3 K and 75.4 K (n, p). Nanosheet rises 74 K and 80.5 K
Shahin et al. (2026)	TCAD, calibrated to measurements, devices biased on individually	2-tier rises 62 K and 74 K. Upper tier of a 4-tier stack rises 83.5 K and 98.5 K
Jang et al. (2021)	TCAD inverter, n-to-p gap cut from 30 to 10 nm	11.9% higher frequency, 3.4% lower dynamic power, 11.2% larger temperature rise

The first two rows come from one paper, and the contrast is the lesson. Under steady bias, the CFET looks far hotter. In a switching inverter it runs slightly cooler, which the authors put down to larger on-current and shorter switching. So one peak temperature in a slide tells you little until you know the bias, the load and the activity. Even so, the same authors conclude that self-heating moves CFET logic gate transient behaviour by up to 15.3% and ring oscillator frequency by up to 7.29%, both worse than nanosheet.

The effect also reaches reliability. Deshwal et al. (2025) found similar bias temperature instability in both devices, but stronger hot carrier degradation in CFET, driven mainly by stronger self-heating.

The Jang result shows a design conflict inside the stack: a smaller vertical gap helps speed and power and hurts temperature. A later paper, Jung et al. (2022), reports only a negligible thermal penalty for a similar move, so the size of this trade is unsettled. Imec suggests a highly conductive backside dielectric may ease the thermal concern, and that is still a proposal.

Density makes it worse. At equal power per cell, 16,632 ÷ 12,096 means 37.5% higher power density at cell level in our example. Imec's own scaling work is framed around a constrained power density budget, and it describes A7 ring oscillator performance as comparable to an N2 nanosheet node. So the first CFET is a density play, and speed is what has to be defended.

We charge this stop as 5% average upsizing, which is the illustrative cost of holding timing against heat and resistance. Block area becomes 18,609 × 1.05 = 19,540 nm². The saving is now 11.9%.

The closing account

Stop	Area per cell	Saving against nanosheet	Points spent
Perfect stack, 2.75T	8,316 nm², against 16,632	50.0%
Height, 4T	12,096 nm², against 16,632	27.3%	22.7
Contacts and routing, 65% utilisation	18,609 nm² of block, against 22,176	16.1%	11.2
Self-heating and drive, 5% upsizing	19,540 nm² of block, against 22,176	11.9%	4.2

Block power density at equal cell power is 22,176 ÷ 19,540, or about 13.5% higher. And because 1 ÷ 0.881 is about 1.135, a CFET wafer costing more than about 13.5% above the nanosheet wafer would raise cost per function, before counting yield. We found no published wafer cost we could trace, so this is a break-even to test and not a forecast.

How to read the next CFET claim

1. What is the baseline? Against single-row CFET, nanosheet or forksheet, and at which node? Imec's 15% and its more than 40% SRAM savings are against different references.
2. Is it cell or block? A cell figure says nothing about utilisation. Lu et al. got block-level figures by running place and route on a RISC-V core.
3. Which cells? A simple gate and a flip-flop can differ by a whole gate pitch.
4. Was the thermal run steady or switching? Ask for the load, activity and heat sink assumption.
5. What did the contacts assume? Check whether backside contact resistance and yield are measured or assumed.

These decisions land early in a chip programme, around node selection and library evaluation. Our SoC lifecycle on The Semiconductor Hub shows where they fall.

FAQ

Does the nFET always go on top?

No. Imec's hybrid channel work and the Miao model place the nFET on top, while the 2026 VLSI tipsheet describes Intel's stack as PMOS on NMOS.

What is the difference between monolithic and sequential CFET?

Monolithic builds both devices on one substrate from a single tall stack. Sequential bonds a second semiconductor layer over finished bottom devices. Imec calls monolithic the least disruptive and fastest route, and notes that wafer distortion from flipping makes front-to-back alignment hard for sequential flows.

Does CFET need backside power?

Not by definition, since imec has shown front-patterned contacts. But its studies, Intel's 2026 paper and the Lu et al. baseline all lean on the wafer back, and imec links backside connections directly to further height reduction. Our post on backside power delivery covers what that route asks of a design team.

Sources

• imec, "Towards a process flow for monolithic CFET transistor architectures", 19 June 2023.
• imec, "Imec demonstrates functional monolithic CFET devices with stacked bottom and top contacts", 19 June 2024.
• imec, "Performance boosters to scale monolithic CFET across multiple logic technology nodes", 26 February 2026.
• imec, "Advancing the CFET-based device roadmap: novel integration modules and standard cell configurations", two articles, 7 September and 6 October 2026, citing Sheng et al., VLSI 2026.
• S. K. Moore, "Intel, Samsung, and TSMC Demo 3D-Stacked Transistors", IEEE Spectrum, 16 December 2023.
• imec, "Imec proposes double-row CFET for the A7 technology node", IEDM 2024 announcement, as carried by Electronic Specifier and reinraum.de.
• eeNews Europe, "IEDM: CFETs make progress at 5nm and 7 angstrom", 11 October 2024.
• 2026 Symposium on VLSI Technology and Circuits, Technical Tipsheet, April 2026, listings for Hwang et al. (Samsung) and Wiedemer et al. (Intel).
• Lu et al., "A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-sided Signals", arXiv:2501.15275, January 2025.
• Choi et al., "Omni 3D: BEOL-Compatible 3D Logic with Omnipresent Power, Signal, and Clock", arXiv:2409.16608, September 2024.
• Shahin et al., "Self-Heating and Parasitic Effects in Multi-Tier CFET Design", arXiv:2603.21910, March 2026.
• Miao et al., "A Novel Thermal Network Model and Electro-Thermal Coupling Study for NSFETs and CFETs Considering Thermal Crosstalk", arXiv:2506.12264, 2025.
• Deshwal et al., "Impact of Aging, Self-Heating and Parasitics Effects on NSFET and CFET", IEEE JxCDC, October 2025.
• Jang et al., "Electrothermal Characterization and Optimization of Monolithic 3D Complementary FET (CFET)", IEEE Access, vol. 9, 2021, and Jung et al., "Device Design Guidelines of 3-nm Node Complementary FET (CFET) in Perspective of Electrothermal Characteristics", IEEE Access, 2022.

The worked example uses illustrative numbers. Vendor and research figures are the organisations' own claims and results, many of them simulated, as published on the dates shown.