Final test, also called end-of-line (EOL) or package test, is the last production test a chip goes through before it is shipped. It is run on every fully assembled, packaged device on automatic test equipment (ATE), usually at one or more temperatures, to confirm that the part still works after packaging, meets its data sheet limits, and belongs in the right speed or quality bin. It is the final gate between the factory and the customer.
In the context of silicon testing, end-of-line testing is a critical step in manufacturing silicon chips and integrated circuits. It is performed on fully assembled devices that have already been packaged, and its purpose is to verify that they meet their specified requirements and are free of defects before they are shipped to customers.
Key takeaways
- Final test happens after assembly, so it catches defects that wafer sort cannot: damage from dicing, wire bonding, bumping, moulding or substrate faults.
- It combines functional (mostly structural scan and BIST), parametric and temperature or stress screening, and it sorts parts into bins.
- Only packaged parts can be tested at full I/O speed and with final thermal behaviour, so many at-speed and analogue tests live here.
- Reliability qualification (such as HTOL) is a sample-based activity; final test applies short screens to every unit.
- A typical flow is: final test, optional burn-in and retest, optional system-level test, then quality assurance sampling and packing.
How final test differs from wafer sort
Production testing has two main insertions. The overview is in What is Silicon Production Testing? The table below compares them.
| Aspect | Wafer sort (probe) | Final test (end of line) |
|---|---|---|
| Device under test | Bare die on the wafer | Packaged part in a socket |
| Contact | Probe card on pads or bumps | Handler and test socket on package pins or balls |
| Main aim | Remove bad die before paying for packaging | Prove the shipped part is good and bin it |
| Speed limits | Probe parasitics limit high-speed I/O tests | Full-speed I/O and SerDes tests possible |
| Temperature | Often one temperature, sometimes hot | Commonly hot and cold, depending on grade |
| Defects caught | Fab defects | Fab escapes plus assembly defects |
What final test checks
End-of-line testing typically includes a combination of functional, parametric and stress testing.
Functional and structural tests
The devices run a series of tests to verify they perform their intended functions correctly. For digital logic, most of the coverage comes from scan-based ATPG patterns (stuck-at and transition-delay faults) and memory BIST, with a smaller set of functional patterns for interfaces, clocking and analogue blocks. Speed binning runs selected patterns at several frequencies or voltages to find the grade each part can sell at.
Parametric tests
The devices are tested for key electrical parameters: continuity and opens and shorts, leakage, supply current (including IDDQ), output drive levels, input thresholds, timing, and for analogue and mixed-signal parts, gain, offset, noise and linearity. Pin capacitance, which the original post listed, is normally characterised on samples rather than measured on every unit.
Temperature and stress screening
The original post described reliability testing on the devices under temperature, voltage and stress conditions to simulate real-world operation. In practice there are two separate things. Final test applies short screens to every unit: test at the hot and cold limits of the grade, voltage margin tests, and, for products that require it, burn-in followed by retest. Long reliability tests that simulate years of use (for example HTOL to JEDEC JESD47, temperature cycling, humidity tests) are run on qualification sample lots before volume release, not on each shipped part.
A typical end-of-line flow
- Final test 1 (FT1), often at hot temperature, full programme.
- Burn-in, where required (common for automotive and some server parts), to trigger early-life failures.
- Final test 2 (FT2), often at cold or room temperature, to catch parts damaged or weakened by burn-in and to confirm cold behaviour.
- System-level test (SLT), for complex SoCs: the part boots an operating system on an application-like board.
- Quality assurance (QA) sample: a sample of passing parts is re-tested on a separate setup to confirm the main test is correct.
- Visual inspection, marking, tape and reel, and shipment.
Temperature limits depend on the product grade. As a common example, AEC-Q100 Grade 1 automotive parts are specified from -40 to +125 degrees C ambient, so their final test usually covers both ends.
Worked example: binning a batch
The numbers below are illustrative. A lot of 10,000 packaged processors goes through FT1 and FT2:
| Bin | Meaning | Count | Share |
|---|---|---|---|
| Bin 1 | Pass at top frequency | 7,200 | 72.0% |
| Bin 2 | Pass at lower frequency grade | 2,100 | 21.0% |
| Bin 5 | Fail, opens or shorts (often assembly) | 150 | 1.5% |
| Bin 6 | Fail, scan or BIST | 350 | 3.5% |
| Bin 8 | Fail, leakage or IDDQ | 200 | 2.0% |
Final test yield is 93 percent, of which 72 percent sells at the top price. A sudden rise in Bin 5 points to the assembly line; a rise in Bin 8 points back to the fab. This feedback is a large part of the value of end-of-line test.
Why end-of-line test matters
End-of-line testing ensures that only high-quality, functional devices are shipped to customers. By identifying and removing defective devices, it reduces the risk of product failures in the field, improves customer satisfaction and minimises the cost of returns and warranty claims. A part caught at final test costs the price of the die and package; the same part failing on a customer's board, or in a car, costs many times more.
Common mistakes
- Relying on wafer sort alone. Assembly adds its own defects, so final test is not optional for most products.
- Poor tester correlation. If two testers or sites disagree, good parts are scrapped or bad parts escape. Correlation units and guard bands keep sites aligned.
- Socket and contact issues. Worn sockets cause false fails and retests; tracking contact resistance and retest rates is standard practice.
- Testing only at room temperature. Many timing and leakage failures appear only at the temperature extremes.
FAQ
Is final test the same as end-of-line test?
In semiconductor manufacturing the terms are used for the same step: the last electrical test on packaged parts before shipping. Some board and system makers also use "end of line" for the last test of their own assembled product.
Who runs final test?
Often an outsourced assembly and test company (OSAT), using a test programme written by the chip company's product and test engineers.
How long does final test take?
From well under a second for simple parts to minutes for large SoCs, and longer when system-level test is added. Multi-site testing spreads the cost across several parts tested in parallel.
Does final test check reliability?
It screens for weak parts with temperature, voltage and, where needed, burn-in. Lifetime reliability is demonstrated separately on qualification samples.
Your comments will be moderated before it appears here.