A SerDes (serialiser/deserialiser) can recover its data in two broad ways. A classic analog SerDes shapes and slices the signal with continuous-time circuits: transmit pre-emphasis, a CTLE, a small DFE and an analog clock and data recovery loop. A DSP-based SerDes digitises the received signal early with a fast ADC and does most of the equalisation, timing recovery and detection in digital logic. Analog designs still win on power and latency for short, clean links, but at 112 Gb/s and 224 Gb/s per lane with PAM4 signalling over lossy copper, ADC and DSP receivers have become the usual choice.
Autonomous vehicles move large volumes of sensor data, data centres shuttle AI workloads between accelerators, and 8K video streams are routine. Every one of these depends on the SerDes, the block that turns wide parallel buses into fast serial streams for cables, PCB traces or optical fibre, and back again. This post explains what each approach does, where each one runs out of road, and how to choose.
Key takeaways
- Channel loss, inter-symbol interference (ISI), noise and jitter set the limits of any high-speed link. Equalisation is how a SerDes fights back.
- Analog SerDes uses pre-emphasis, CTLE, DFE and an analog CDR. It is low latency and power-efficient for moderate data rates and moderate loss.
- DSP SerDes puts a DAC on the transmit side and an ADC plus digital FFE, DFE, possibly MLSE, timing recovery and FEC on the receive side. It adapts better and scales with process technology.
- PAM4 carries 2 bits per symbol, halving the symbol rate for a given bit rate, but its eyes are one third the height of NRZ, a signal-to-noise penalty of about 9.5 dB.
- Most 112G and 224G long-reach electrical links today use ADC and DSP receivers; many short-reach links (die-to-die, chip-to-module) still use mostly analog designs to save power.
The challenges of high-speed data transmission
Before comparing architectures, it helps to be clear about what a multi-gigabit link is fighting.
Signal integrity degradation
- Channel loss: high-frequency energy is attenuated by copper traces, connectors and cables, mostly through skin effect and dielectric loss. The original version of this post gave the example of about 24 dB loss at 12 GHz for a 15 m automotive coax; treat that as an indicative figure, since real loss depends heavily on the cable type.
- Inter-symbol interference (ISI): energy from earlier symbols smears into the current one (post-cursor ISI), and the channel's group delay can also put energy ahead of the main cursor (pre-cursor ISI).
- Noise and jitter: EMI, crosstalk from neighbouring lanes, power supply noise and clock imperfections all close the eye.
Bandwidth demands
8K video, AI clusters and highly automated vehicles keep pushing per-lane rates up. PCIe 6.0 runs at 64 GT/s per lane using PAM4, and Ethernet and OIF electrical interfaces run at 112 Gb/s per lane, with 224 Gb/s per lane now being deployed. (The original post cited PCIe 6.0 as an example of 100+ Gb/s per lane; strictly it is 64 GT/s per lane per direction, so the 100 Gb/s class examples are Ethernet and OIF links.)
Power and cost constraints
Analog circuits do not scale gracefully. At advanced nodes such as 3 nm, supply headroom shrinks and device matching gets harder, so precision analog blocks become costly to design and do not shrink much. Digital logic, by contrast, gets smaller and lower power with every node, which is one of the main reasons the industry has moved towards DSP.
Pure analog SerDes: simplicity meets limitations
A traditional analog SerDes relies on amplifiers, filters and comparators to shape and recover the signal without ever converting it to a multi-bit digital word.
How it works
- The transmitter uses a short FIR filter (pre-emphasis or de-emphasis) to boost high frequencies relative to low ones.
- The receiver uses a continuous-time linear equaliser (CTLE) to undo part of the channel's low-pass shape, often followed by a few taps of decision feedback equalisation (DFE).
- A clock and data recovery (CDR) loop, often a bang-bang phase detector driving a phase interpolator, places the sampling point.
- Modulation is typically NRZ (PAM2), one bit per symbol.
Pros
- Low latency: there is almost no processing pipeline, so data comes out within a few unit intervals.
- Low power: minimal digital logic suits simple links such as USB 2.0 and SATA, and modern short-reach links.
Cons
- Fixed functionality: the equaliser structure is tuned for a narrow range of channels and protocols, with little room for multi-standard support.
- Limited adaptability: it struggles with changing channel conditions, such as temperature shifts in automotive systems.
- Scalability wall: the original post said NRZ hits a wall at about 10 Gb/s. That figure is too low: NRZ is used at 25 to 28 Gb/s in Ethernet and at 32 GT/s in PCIe 5.0. What is true is that above roughly 50 Gb/s per lane, NRZ needs too much channel bandwidth for practical copper, which is why PAM4 took over.
Example: legacy automotive camera links such as GMSL1 and GMSL2 carrying 1080p video.
DSP-based SerDes: the digital approach
A DSP-based SerDes replaces most of the analog signal shaping with algorithms. By digitising the signal early and using programmable logic, it can apply long equalisers, adapt continuously and support several standards from one design.
Architecture breakdown
- Analog front end (AFE): kept as small as possible: a DAC and driver on transmit, and a variable-gain amplifier, a light CTLE and a time-interleaved ADC on receive (typically 6 to 8 bits effective at the symbol rate).
- Digital signal processor: handles equalisation, clock recovery, detection and error correction in algorithms.
DSP-based SerDes block diagram
Courtesy: Alphawave Semi
Key DSP algorithms
- Adaptive equalisation (FFE and DFE): a feed-forward equaliser with many taps cancels pre-cursor and post-cursor ISI, and a DFE removes post-cursor ISI using past decisions. The taps adapt continuously, usually with a least-mean-squares (LMS) algorithm.
- MLSE (Viterbi algorithm): maximum-likelihood sequence estimation decides on the most likely sequence of symbols rather than one symbol at a time, which helps on channels with heavy residual ISI or noise.
- PAM4 and PAM8 modulation: encode 2 or 3 bits per symbol, doubling or tripling the bits carried per unit of bandwidth.
- Forward error correction (FEC): Reed-Solomon or LDPC codes correct errors without retransmission. Ethernet at 100G per lane uses RS(544,514), often called KP4 FEC.
Why NRZ gives way to PAM4: a worked example
Take a 112 Gb/s lane. The numbers below are standard arithmetic; the loss figures are illustrative.
| Item | NRZ (PAM2) | PAM4 |
|---|---|---|
| Bits per symbol | 1 | 2 |
| Symbol rate for 112 Gb/s | 112 GBd | 56 GBd |
| Nyquist frequency | 56 GHz | 28 GHz |
| Eye height relative to NRZ | 1 | 1/3 (three eyes stacked) |
| SNR penalty | 0 dB | about 9.5 dB (20 log10 3) |
| Illustrative channel loss at Nyquist | roughly twice the dB of PAM4, since loss in dB grows close to linearly with frequency | around 30 dB for a long-reach backplane |
PAM4 halves the Nyquist frequency, which roughly halves the channel loss in dB, at the cost of a 9.5 dB smaller eye. On a lossy copper channel the loss saving is larger than the penalty, which is why PAM4 won. The price is that the receiver must resolve four levels with good linearity, which is where an ADC and digital equaliser become attractive: a long FFE in digital logic is far easier to build, adapt and verify than an equivalent analog filter.
The original post said PAM4 enables 56 Gb/s, and PAM8 112 Gb/s, in the same Nyquist bandwidth as 28 Gb/s NRZ. The PAM4 half is right (28 GBd carrying 2 bits gives 56 Gb/s). PAM8 carries 3 bits per symbol, so at the same 28 GBd it gives 84 Gb/s, not 112 Gb/s.
Why DSP dominates modern systems
Channel agnosticism
A DSP receiver auto-calibrates for different cable lengths, temperatures and interference, and keeps adapting while the link runs. The original post gave the example of GMSL4 adjusting to a 15 m automotive coax at 24 Gb/s with PAM4; treat that product detail as reported and check the current Analog Devices data before relying on it.
- Multi-protocol flexibility: one DSP SerDes can support PCIe, Ethernet or other protocols by changing firmware and configuration, as long as the analog front end covers the required rates.
- Higher data rates: PAM4 with strong digital equalisation reaches 112 Gb/s and 224 Gb/s per lane over channels that NRZ could not use.
- Power efficiency: a DSP can scale its equalisation effort, for example turning off FFE taps and MLSE on a short, clean link to save power.
Head-to-head comparison
The same comparison in text, with a few extra rows:
| Aspect | Analog SerDes | DSP-based SerDes |
|---|---|---|
| Typical modulation | NRZ, some PAM4 | PAM4, with PAM6 and PAM8 studied |
| Equalisation | TX FIR, CTLE, few-tap DFE | TX FIR, long digital FFE, DFE, optional MLSE |
| Latency | Very low, a few UI | Higher, tens of nanoseconds including DSP pipeline and FEC |
| Power on short, clean links | Lowest | Higher, unless blocks are switched off |
| Power on long, lossy links | Struggles or cannot close the link | Better energy per bit at 112G and above |
| Adaptability | Limited | Continuous adaptation, rich diagnostics |
| Process scaling | Poor, analog does not shrink much | Good, most area is digital |
| Design and verification | Analog-heavy, sensitive to corners | ADC is hard; the DSP can be verified like any digital block |
Real-world applications
- Automotive (GMSL and similar camera links): DSP-style equalisation helps high-resolution cameras and sensor fusion links cope with long coax, connectors and a noisy, vibration-prone environment.
- Data centres (800G Ethernet): PAM4 DSPs drive 800G optical modules and their electrical host interfaces. The original post said this reduces per-bit power by 30% compared with analog NRZ; that figure has not been re-verified and should be read as an indicative claim.
- AI and ML hardware: NVIDIA quotes 900 GB/s of coherent bandwidth for the NVLink-C2C connection between the Grace CPU and Hopper GPU in its Grace Hopper Superchip. Whether that short-reach PHY is DSP-based is not publicly detailed, so it is better read as an example of the bandwidth AI systems demand than as proof of DSP use.
Common mistakes when comparing the two
- Assuming DSP always costs more power. At 112G long reach, an ADC and DSP receiver can use less energy per bit than an analog design pushed to its limits.
- Assuming analog is obsolete. Die-to-die links (UCIe, for example) and many chip-to-module links are short enough that simple, mostly analog transceivers are the right answer.
- Ignoring latency. FEC and DSP pipelines add delay. For memory-semantic links and some AI fabrics, a few tens of nanoseconds matter.
- Quoting bit rate and symbol rate interchangeably. 112 Gb/s PAM4 is 56 GBd; channel loss must be read at the Nyquist frequency of the symbol rate.
The future: beyond PAM4
224 Gb/s per lane and 1.6T Ethernet: IEEE 802.3dj and the OIF CEI-224G work use PAM4 at about 112 GBd for 200 Gb/s class electrical lanes. The original post expected PAM8 to deliver 200 Gb/s per lane; the current standards chose PAM4 instead, with PAM6 and PAM8 still studied for later generations. Higher-order PAM shrinks the eye further: PAM8 eyes are one seventh the height of NRZ, which is why it has not been adopted yet.
Optical DSP integration: co-packaged optics (CPO) and linear-drive optics try to cut power by moving the optics next to the switch or removing the module DSP altogether, which shifts the equalisation burden onto the host SerDes.
AI-assisted SerDes: researchers are studying neural-network equalisers and machine-learning-based adaptation. These are research topics today, not shipping replacements for FFE, DFE and MLSE.
The analog sunset?
Analog SerDes still serves low-speed and short-reach applications well, and every DSP SerDes still depends on excellent analog design in its ADC, DAC, PLL and drivers. But for long-reach links at 112G and above, DSP-based designs have become the core of modern connectivity. By combining algorithmic flexibility with mixed-signal hardware, they deliver the speed, efficiency and adaptability that AI-scale systems need. As the industry moves to 224 Gb/s PAM4 and beyond, the direction is clear: the future of high-speed SerDes is increasingly digital.
FAQ
Is a DSP SerDes fully digital?
No. It still needs a high-speed DAC, ADC, PLL, driver and termination. "DSP-based" means equalisation and detection happen mainly in the digital domain after the ADC.
Why does PAM4 need FEC?
The smaller PAM4 eye leads to a raw bit error rate of around 1e-5 to 1e-4 at the slicer, far above what applications accept. FEC such as RS(544,514) corrects these errors to an effective error rate many orders of magnitude lower.
What does an analog SerDes do better?
Latency and power on short, clean channels. A die-to-die or short chip-to-chip link rarely needs a long equaliser.
What does MLSE add over a DFE?
A DFE makes one decision at a time and can propagate errors. MLSE considers whole sequences of symbols and picks the most likely one, which recovers margin on channels with strong residual ISI.
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