Top 50 Physical Design Interview Questions with Answers

Physical design interviews test whether you can take a synthesised netlist to a clean, sign-off ready layout: floorplanning, power planning, placement, clock tree synthesis, routing, timing closure and physical verification. The 50 questions below are the ones that come up most often, from basic concepts to tape-out, each with a short model answer. Use them to check your own answers, then expect the interviewer to push for numbers, trade-offs and a real example from your work.

Physical design is one of the most demanding areas of VLSI (very large scale integration) design, and demand for good physical design engineers keeps rising as chips get smaller, faster and more complex. Physical design translates a circuit netlist into a geometric layout that can be fabricated on silicon. It includes floorplanning, placement, clock tree synthesis, routing and timing analysis, and each step needs careful attention to detail and a solid grasp of the concepts and tools behind it. Whether you are a recent graduate trying to enter the field or an experienced engineer preparing for your next move, these questions cover the range an interview panel will draw from.

Key takeaways

• Know the flow end to end and the inputs and outputs of each step.
• Setup and hold fixes are different problems: setup is about the slowest path, hold about the fastest, and only setup depends on clock frequency.
• Power integrity (IR drop and electromigration) and signal integrity (crosstalk) are sign-off checks, not afterthoughts.
• At advanced nodes, multi-patterning, variation and wire resistance drive many of the problems.
• Good answers name the trade-off and give a number.

Flow and fundamentals

1. Can you explain what physical design in the VLSI industry involves and why it matters?
   It converts a gate-level netlist into a layout (GDSII or OASIS) that meets timing, power, area and manufacturing rules. It matters because this is where the design meets real wires, real parasitics and real process rules: a correct netlist can still fail on silicon if the physical implementation is poor.
2. Describe the key responsibilities of a physical design engineer in the design flow.
   Floorplanning, power planning, placement, CTS, routing, timing closure with the STA team, physical verification (DRC, LVS, antenna, ERC), power integrity, ECOs and the final database hand-off. The PD engineer also feeds back to RTL and synthesis teams when a block cannot close.
3. Describe the process of creating a physical design database.
   Load the technology file and physical libraries (LEF or equivalent), timing libraries (Liberty) for each corner, the netlist, SDC constraints, RC extraction models and, if used, scan DEF and UPF power intent. Link the design, check for missing cells and unresolved references, define corners and modes, and save the starting database.
4. What tools are commonly used in physical design, and which ones are you proficient with?
   Typical tools are Synopsys Fusion Compiler and IC Compiler II, or Cadence Innovus, for implementation; PrimeTime or Tempus for timing sign-off; StarRC or Quantus for extraction; RedHawk-SC or Voltus for power integrity; and Calibre, IC Validator or Pegasus for physical verification. Answer honestly about which you have used, and on what kind of design.

Floorplanning and power

5. Describe your approach to floorplanning.
   Estimate core area from cell and macro area at a starting utilisation, often 60 to 75%. Place macros along the data flow with pins facing the core, leave routing channels, add halos, place pins, build the power grid and run a trial placement to check congestion and timing before committing.
6. What guidelines do you follow for macro placement?
   Keep macros near the logic and pins they talk to, usually at the edges; avoid narrow channels and notches; align macros to make clean power connections; keep memories of the same bank together; and leave enough space at macro pins for routing.
7. How do you design an effective power grid or power distribution network (PDN)?
   Start from the power budget and the allowed IR drop. Add core rings or bump connections, wide straps on the top thick metals, a mesh on intermediate layers and standard cell rails on the lowest metal, with enough vias between layers. Choose strap width and pitch from IR and electromigration analysis, then verify statically and dynamically and refine where hot spots appear.
8. What is IR drop, and why is it crucial in VLSI design?
   It is the voltage lost across the resistance of the power grid when current flows (V = I x R). Cells see a lower supply than nominal, so they slow down and may fail timing or even function. Teams set an IR drop budget, typically a few percent of the supply, and timing analysis must reflect it.
9. What is the difference between static and dynamic IR drop?
   Static IR uses average current and shows whether the grid is strong enough overall. Dynamic IR uses switching current over time and shows local dips when many cells switch together, which decap cells and spreading of high-activity cells address.
10. How do you manage electromigration issues?
    Electromigration is the slow movement of metal atoms under high current density, which can open or short wires over time. Check current density against foundry limits for power and signal nets, then widen wires, add vias, use non-default rules on high-current nets, and limit drive strength or fanout on signal nets that fail.

Placement

11. What are the key considerations in the placement stage?
    Timing-driven placement of critical paths, congestion, cell density, keeping placement legal on rows and sites, scan chain reordering, and leaving room for CTS and later optimisation.
12. How do you handle congestion issues?
    Find the cause first: high local density, macro channels, high pin density cells or a poor floorplan. Fixes include partial placement blockages, cell padding, spreading high pin density cells, moving macros, adjusting pin placement and, if needed, asking synthesis to restructure the logic.
13. What do utilisation and density mean, and what values do you aim for?
    Utilisation is cell area divided by available core area. Too high and the design will not route or close timing; too low and area is wasted. Starting values vary by design and node, and local density limits matter as much as the overall figure.

Clock tree synthesis

14. Can you walk me through clock tree synthesis (CTS)?
    Set targets for skew, latency and transition, choose clock buffers and inverters and routing rules, define exceptions, build the tree, optimise it, route the clock nets and then switch timing analysis from ideal to propagated clocks. After CTS, fix the hold violations that the real tree reveals.
15. What techniques do you use to manage clock skew?
    Balanced tree topologies, clock mesh or multi-source CTS for large high-speed designs, non-default rules (wider, spaced or shielded wires) to reduce variation, a single Vt flavour for clock cells, and grouping sinks that talk to each other.
16. What is the difference between skew, latency and jitter, and what is useful skew?
    Latency is the clock delay from source to a sink. Skew is the difference in latency between two sinks. Jitter is variation in the clock edge from cycle to cycle. Useful skew deliberately delays or advances a clock to borrow time for a critical path from a neighbouring path with slack.

Timing

17. How do you tackle setup timing violations?
    Look at the path first: cell delay, wire delay or clock. Then upsize or swap to lower Vt cells, buffer long wires, move cells closer, restructure logic, use useful skew, or move layers for lower resistance. If the path is architectural, it goes back to RTL.
18. What strategies do you use to fix hold violations?
    Add delay to the data path with buffers or delay cells, downsize or swap to higher Vt cells on the fast path, or adjust clock skew. Hold fixes must not break setup, so check both. Hold does not depend on clock frequency: a hold failure on silicon cannot be fixed by slowing the clock.
19. What is timing closure, and how do you achieve it?
    Timing closure means all setup, hold, transition, capacitance and other timing checks pass in all sign-off corners and modes. It is achieved by iterating between implementation and sign-off STA, with good constraints from the start, and by fixing in the order that hurts least: placement and floorplan first, then sizing, then ECOs.
20. What are on-chip variation (OCV), AOCV and POCV?
    OCV applies flat derates to early and late paths to model variation across the die. AOCV makes the derate depend on path depth and distance. POCV (or parametric OCV) models delay as a statistical distribution per cell, which is less pessimistic and is standard at advanced nodes.
21. What is multi-mode multi-corner (MMMC) analysis?
    Timing is checked in every combination of functional or test mode and process, voltage, temperature and RC corner that matters. Setup usually worsens at the slow corner and hold at the fast corner, but temperature inversion at advanced nodes can make cold the slow corner, so corners are chosen with care.

Routing and signal integrity

22. Can you explain the routing process?
    Global routing divides the die into tiles and assigns nets to regions and layers to estimate congestion. Track assignment places nets on tracks. Detailed routing creates the exact wires and vias that meet all design rules. Search and repair then removes the remaining violations.
23. What techniques do you use for post-route optimisation?
    Sizing and Vt swaps, buffering, hold fixing, crosstalk fixes, layer changes for critical nets, redundant via insertion and incremental reroute, all checked with real extracted parasitics.
24. What methods do you use to ensure signal integrity?
    Spacing and shielding for sensitive nets, avoiding long parallel runs, limiting transition times, upsizing weak victim drivers, and routing clocks with non-default rules.
25. What is signal integrity analysis, and how do you conduct it?
    The STA tool, with coupling capacitance from extraction, computes crosstalk delta delay on switching victims and glitch noise on quiet victims, considering aggressor timing windows. Glitches are checked against the noise immunity of the receiving cells.
26. How do you handle crosstalk in your designs?
    Increase spacing, add shields, reroute on different layers, insert buffers to break long coupled runs, upsize victim drivers or slow down aggressors, and fix glitches on clock and reset nets first.
27. What is the antenna effect, and how do you fix it?
    During plasma etch, long metal connected only to a transistor gate collects charge that can damage the gate oxide. Rules limit the ratio of metal area to gate area. Fixes are layer jumping (breaking the wire and finishing it on a higher layer) and antenna diodes near the gate.
28. What is parasitic extraction, and why is it important?
    Extraction calculates the resistance and capacitance of every wire and via from the layout and the process stack. Timing, signal integrity and power analysis all depend on it, so sign-off uses the foundry's qualified extraction decks in every RC corner.

Physical verification

29. Why are Design Rule Checks (DRC) crucial, and how do you perform them?
    DRC checks the layout against the foundry's rules for width, spacing, enclosure, density and more. A violation can cause shorts, opens or low yield, so the foundry will not accept a design with unwaived errors. Run the foundry's sign-off rule deck on the full merged GDS, fix or get approved waivers, and rerun after every change.
30. How would you approach running DRC at lower technology nodes such as 28 nm and below?
    Rule decks grow large and context-dependent, so run DRC early and often, by block and at full chip. Pay attention to density and fill rules, via and end-of-line rules and, where used, multi-patterning colouring checks. Split long jobs across many CPUs.
31. How do you handle design rule violations during the design process?
    Group them by type and cause: many come from one source, such as a macro edge, a pin pattern or a routing rule. Fix in the implementation tool where possible, using its own DRC engine, so later ECOs do not bring the errors back. Use manual fixes only for the last few.
32. What is the significance of layout versus schematic (LVS) checks, and how do you perform them?
    LVS confirms that the layout's devices and connections match the netlist. Shorts, opens and missing connections show up here. Run it with the foundry rule deck, using a netlist that includes physical-only cells such as fillers and decaps, and resolve every mismatch.
33. What role does verification play in physical design, and how do you implement it?
    It proves that the layout is correct, manufacturable and meets its targets: DRC, LVS, antenna and ERC for the layout; logic equivalence for the netlist; STA, IR drop, electromigration and signal integrity for performance and reliability.
34. Do you need a testbench for physical design verification?
    Usually not. Physical design changes the netlist (buffers, sizing, CTS, scan reordering), and correctness is shown by formal logic equivalence checking between the synthesised and final netlists, plus static checks. Gate-level simulation with SDF timing is sometimes run as an extra check on resets, clocking and test modes.
35. Describe your process for creating a test plan for physical design.
    In physical design this is a sign-off checklist: every check, the tool and rule deck version, the corners and modes, the pass criteria and the owner. It is agreed at the start and tracked to tape-out.

Manufacturability, reliability and test

36. How do you ensure manufacturability in your designs?
    Follow the foundry's recommended rules, not just the mandatory ones; insert redundant vias; meet metal and poly density with fill; avoid patterns flagged by lithography checks; and spread wires where space allows.
37. What is Design for Manufacturability (DFM), and why is it significant?
    DFM is a set of practices that improve yield and robustness beyond basic DRC: redundant vias, wire spreading, density balancing, litho hot spot checks and critical area analysis. It matters because a design that is DRC clean can still yield poorly.
38. How do you address thermal issues?
    Spread high-power blocks, use thermal analysis to find hot spots, account for self-heating at advanced nodes, and include the right temperatures in timing and electromigration sign-off. Package and system cooling set the limits.
39. How do you ensure the reliability of your physical designs?
    Sign off electromigration on power and signal nets, IR drop, ESD and latch-up rules, ageing derates in timing where needed, and redundant vias.
40. What is the importance of Design for Testability (DFT) in physical design?
    DFT logic such as scan chains, compression and memory BIST must be placed, routed and timed like functional logic. PD reorders scan chains to save wirelength, closes timing in test modes and keeps test clocks and lock-up latches correct.

Advanced nodes

41. What challenges do you face in lower geometry designs, and how do you overcome them?
    Higher wire and via resistance, multi-patterning, complex rules, more variation, stronger IR and electromigration limits and larger run times. Answers include early power and congestion analysis, layer-aware routing for critical nets, statistical timing and tighter collaboration with the foundry and library teams.
42. What is multi-patterning, and how does it affect physical design?
    When metal pitch is below what one 193 nm immersion exposure can print, roughly 80 nm, a layer is split into two or more masks. Shapes get colours, and same-colour spacing rules apply. Routing must be colour-aware, and some patterns become illegal.
43. What is your approach to creating a layout for a VLSI design?
    Follow the flow: clean inputs, a floorplan that fits the data flow, a robust power grid, timing-driven placement, a good clock tree, routing with SI in mind, then verification and sign-off with ECO loops.
44. How do you ensure the accuracy of your physical design?
    Use sign-off quality tools and decks, correlate implementation timing with sign-off timing, keep constraints and libraries under version control, and automate the checks so nothing is skipped.
45. How do you optimise your design for power and performance?
    Use multi-Vt cells, clock gating, right-sized cells, shorter wires on high-activity nets, power gating where the architecture allows, and useful skew. Measure each change against both timing and power reports.

Tape-out and beyond

46. What role does a physical design engineer play in the tape-out process?
    The PD engineer owns a clean final database: all checks closed or waived with sign-off, the final GDS merged with IP and fill, and the documentation the foundry needs.
47. How do you ensure your design is ready for tape-out?
    Walk the sign-off checklist: timing in all corners, equivalence, DRC, LVS, antenna, ERC, IR, electromigration, density, and confirmation that IP versions and rule decks are the final ones.
48. What are some common issues in physical design, and how do you address them?
    Congestion, timing that does not converge, hold fixes that break setup, IR hot spots, late netlist changes and DRC around macros. The cure is usually earlier analysis and a better floorplan rather than more late fixes.
49. What is an ECO, and how do you implement one?
    An engineering change order changes the design late without restarting the flow. Timing ECOs size or add cells; functional ECOs change logic. After layout freeze, metal-only ECOs use spare cells so only metal masks change.
50. What are the future trends in VLSI physical design, and how do you keep your skills up to date?
    Backside power delivery, gate-all-around transistors, 3D stacking and chiplets, and machine learning in EDA tools. Keep up through vendor training, conference papers (DAC, ISPD, ICCAD), foundry documentation and hands-on practice.

How interviewers probe these answers

• "Give me a number": expect to estimate wire delay, IR drop or utilisation on the spot.
• "What would you do if": for example, setup and hold both fail on the same path, or congestion moves after you fix it.
• "Why that order": why place macros before standard cells, or why fix hold after CTS.
• "Show it on your project": be ready with one hard problem you solved, the data you used and the result.

FAQ

Which topics matter most for a fresher?

The flow, setup and hold, CTS basics, IR drop and DRC and LVS. Panels expect clear concepts more than tool depth.

Which topics matter most for an experienced engineer?

Timing closure strategy, advanced node issues, power integrity, ECOs and how you made decisions on a real tape-out.

Do I need to know scripting?

Yes. Tcl is used in every major implementation tool, and Python or Perl is common for reports and automation.