What Is a PDK, and Why It Is the Silent Backbone of Chip Innovation

A PDK (Process Design Kit) is the package of models, rules, libraries and verification decks that a foundry supplies for one manufacturing process, so that chip designers can simulate, lay out and check a design before it is built. It is the foundry's process described in a form that EDA tools can read. Every chip that reaches silicon, from a smartphone processor to a power converter, was designed against a PDK, which is why it is often called the silent backbone of the industry.

Smartphones, data centres and electric vehicles all run on silicon chips, and designing those chips is one of the hardest jobs in engineering. At the centre of that work is something few people outside the industry have heard of: the PDK.

Key takeaways

• A PDK is specific to one foundry, one process node and often one process option (for example a low-power or RF flavour of the same node).
• Its core contents are device models, design rules, layout and schematic building blocks, verification decks and parasitic extraction rules.
• Simulation is only as good as the PDK's models: if the models are wrong, the silicon will not match the simulation.
• PDKs mature in versions (early, pre-production, production), and designs taped out on early versions carry more risk.
• PDKs now cover RF, analog, photonics and wide-bandgap power processes, and open PDKs such as SkyWater SKY130 let universities and start-ups build real chips.

What a PDK is

PDK stands for Process Design Kit. It is not a single file or program but a package of technology data, models and rules that a foundry supplies for one manufacturing process.

A PDK typically includes:

• Device models: SPICE models that predict how transistors, resistors, capacitors and diodes behave across voltage, current and temperature.
• Design rules: the physical limits that make a layout manufacturable, such as minimum spacing between metal lines or density limits.
• Layout and schematic building blocks: technology files, parameterised cells (PCells) and symbols that let designers draw schematics and layouts quickly. Standard cell libraries usually come alongside, from the foundry or an IP vendor.
• Verification decks: rule files for DRC (design rule check), LVS (layout versus schematic) and ERC (electrical rule check).
• Extraction rules: for parasitic resistance and capacitance, which matter more at small geometries, where wiring can affect performance as much as the transistors.
• Documentation and examples: guides, tutorials and reference flows that help teams use the kit.

Put simply, the PDK is the foundry's process described in a form that design tools can use.

What is inside, and which tool reads it

The table below maps the main parts of a PDK to the tools and design steps that consume them. Exact file formats vary by foundry and EDA vendor.

PDK component	Typical form	Used by
Device models	SPICE model cards (BSIM-family models for MOSFETs and FinFETs), corner and statistical files	Circuit simulators (SPICE, FastSPICE) for analog, custom and cell characterisation
Design rules	Design rule manual plus DRC runsets	Layout engineers and physical verification tools
Technology files and PCells	Layer maps, display files, parameterised device generators	Schematic and custom layout editors
LVS and ERC decks	Rule files for the sign-off verification tool	Physical verification before tape-out
Extraction rules	Interconnect stack and capacitance tables	Parasitic extraction feeding timing, power and post-layout simulation
Digital views (often with the standard cell library)	Abstract layout (LEF), timing and power (Liberty), routing rules	Synthesis, place and route, static timing analysis

Corners and statistics

A PDK does not describe one "typical" transistor. Manufacturing varies from wafer to wafer and die to die, so the models come in process corners, usually named by NMOS and PMOS speed: TT (typical-typical), FF (fast-fast), SS (slow-slow), and the skewed corners FS and SF. These are combined with voltage and temperature to give PVT corners. Many PDKs also include statistical (Monte Carlo) models for local mismatch, which analog designers rely on to size matched pairs and current mirrors.

An illustrative example: a digital block might be signed off at the SS corner, 0.9 times nominal supply and 125 °C for setup timing, and at the FF corner, 1.1 times nominal supply and minus 40 °C for hold timing. The exact corner set is defined by the foundry and the product's requirements, not by a universal rule.

Why PDKs matter

Without a PDK, a designer could draw circuits that cannot be built. The PDK sets the rules for that specific process.

Simulation depends on the device models in the PDK. If the models are wrong, the silicon will not behave as simulated, and the error is repeated across every chip that is made.

Ready-made building blocks and automated checks also save design teams from starting from scratch, which is what makes large chip projects possible on tight schedules.

A new kit for each node. Every new process node, for example 7 nm, then 5 nm, then 3 nm, comes with its own PDK. The kit evolves with the manufacturing process so designers can push performance and power efficiency further.

PDK versions and maturity

A PDK for a new node is released in stages. Early versions (often numbered 0.1 or 0.5) are based on test structures and simulation, and the models and rules can still change. A production version (often 1.0 and later) is based on silicon data from the qualified process. Foundries number and name these stages in their own way, but the principle is the same: a design started on an early PDK must be re-checked as the kit matures, and late rule or model changes are a known source of schedule risk.

How a PDK fits into the design flow

1. Selection: the team chooses a foundry, node and process option, then signs the agreements needed to receive the PDK.
2. Set-up: the CAD team installs the PDK, checks it against the EDA tool versions the foundry has qualified, and builds the project environment.
3. Design: analog and custom designers simulate with the device models and draw layout with the PCells; digital teams use the standard cell libraries built on the same PDK.
4. Verification: layouts are checked with the DRC, LVS and ERC decks, and parasitics are extracted for post-layout simulation and timing.
5. Sign-off and tape-out: the final layout must be clean against the PDK version the foundry accepts for that tape-out.

PDKs beyond digital CMOS

PDKs were built mainly for digital CMOS logic. Their scope is now much wider:

• RF and analog PDKs support 5G, IoT and advanced sensing.
• Photonic PDKs support silicon photonics for fast data links in AI clusters and data centres.
• Wide-bandgap PDKs for GaN and SiC support electric vehicles, renewable energy and efficient power supplies.

Open PDKs are growing too. The SkyWater 130 nm open PDK (SKY130), released in 2020 with Google's support, lets start-ups, universities and hobbyists design and fabricate real chips. It has since been joined by other open kits, including GlobalFoundries' 180 nm GF180MCU and IHP's 130 nm SiGe BiCMOS kit, which work with open-source flows such as OpenROAD and OpenLane as well as commercial tools.

Challenges

• Complexity: as nodes shrink, PDKs grow more intricate and need larger teams to maintain and validate them. Multi-patterning, FinFET and gate-all-around devices, and layout-dependent effects all add rules and model terms.
• Differentiation versus standards: foundries want PDKs that show off their processes, but customers and EDA vendors want common formats. Efforts such as the interoperable PDK (iPDK) work aim to let one kit run on tools from several vendors.
• Openness versus protection: sharing enough for design while protecting sensitive foundry data remains a balancing act. Most advanced-node PDKs are available only under non-disclosure agreements.

How the industry handles these will affect the pace of chip innovation over the next decade.

Common mistakes with PDKs

• Mixing versions: using models from one PDK release with DRC decks or libraries from another. Every view should come from the same, recorded version.
• Using unqualified tool versions: foundries qualify their decks against specific EDA releases. A newer tool is not automatically safe.
• Simulating only the typical corner: a circuit that works at TT can fail at SS and high temperature, or leak too much at FF.
• Ignoring PDK release notes: rule and model changes between versions are listed there, and they decide what must be re-verified.

Why it matters beyond the lab

The PDK is what connects foundries, EDA tool vendors and design teams, so a chip can move from concept to volume production without surprises. Users never see it, but it is essential.

Every AI accelerator, self-driving chip and low-power IoT sensor on the market depended on a PDK doing its job in the background.

FAQ

Is a PDK the same as a standard cell library?

No. The PDK describes the process itself: devices, rules and checks. A standard cell library is a set of pre-designed logic gates built and characterised using that PDK. It often ships with the PDK, but it can also come from a third-party IP vendor.

Who creates the PDK?

The foundry owns the process data and is responsible for the PDK, usually working with EDA vendors so that the decks and models run correctly in their tools.

Can I get a PDK without a foundry contract?

For advanced commercial nodes, generally no. Open PDKs such as SKY130 and GF180MCU are freely downloadable and are a good way to learn the full flow.

Why does a new node need a new PDK?

Each node has different devices, layers, rules and parasitics. The models and rules of one node do not describe another, so the kit has to be rebuilt and re-validated for each process.