What One High-NA Exposure Has to Earn: A Cost-per-Layer Calculation

A high-NA EUV scanner costs far more to run per wafer than a low-NA one, yet it can still win on the layers where it replaces several exposures. In the illustrative model below, one high-NA pass costs about 2.3 times one low-NA pass at the scanner, but the finished layer comes out at about €176 per wafer against about €222 for two low-NA passes.

That margin is much less secure than it looks. It falls to about €10 once a large die needs stitching, and it reverses for a stitched die at low volume, where two high-NA masks per layer are hard to pay for. This post sets out the calculation so you can rerun it with your own numbers and find where the crossover sits for your layer.

Key takeaways

• Compare whole patterning layers, not scanner passes. Etch, deposition, track and metrology are repeated for every low-NA pass, and in this model they matter more than the scanner on a two-exposure layer.
• With our inputs, high-NA stays cheaper than two low-NA passes down to about 99 wafers per hour, and cheaper than three down to about 57.
• Die size and mask volume together move the answer more than a €100m change in tool price. A die above 429 mm² needs two masks per layer.
• Three-mask and four-mask layers are the safe case. Two-mask layers are close enough that yield and cycle time should decide.
• All cost inputs here are illustrative. The technical figures are vendor and research claims, labelled as such.

What is published, and what is not

The public record is rich on capability and thin on cost. In its first-quarter 2026 investor call, ASML said customers had shown Logic and DRAM cases in which one high-NA exposure replaces three or four low-NA exposures, and that for some critical layers the number of process steps can fall by a factor of 10. These are ASML's own descriptions of customer papers, and they refer to selected layers.

imec's February 2026 review gives specific layers. For A14 and A10 logic M0 and M2, it counts three to four masks at 0.33 NA against one exposure at 0.55 NA. For the BLP/SNLP layer in D1d and D0a DRAM, it counts at least three masks against one. The article states the direction of cost, but gives no figure. Neither ASML's documents nor imec's articles cited here put a price on a patterning layer, which is why the rest of this post uses a labelled model.

Adoption is real but early. The table below keeps the status of each statement visible.

Statement	Who says so	Status
EXE:5200B runs at 175 wafers per hour, 60% above EXE:5000	ASML 2025 Annual Report	Vendor figure
Eight high-NA systems shipped by the end of 2025, six in operation	ASML AGM presentation, April 2026	Vendor figure
More than 500,000 wafers processed, over 80% availability	ASML investor call, April 2026	Vendor figure
Insertion at customers in 2027 to 2028	ASML AGM presentation, April 2026	Vendor expectation
Intel qualified and accepted an EXE:5200B for high-volume use on leading-edge nodes	ASML investor call, January 2026, reporting Intel's announcement	Company statement
EXE:5200B installed at M16, Icheon, with a plan to simplify the existing EUV process	SK hynix, September 2025	Company statement of plan, no results given

The model and its inputs

The unit is one critical patterning layer on one 300 mm wafer. We count three things for each exposure: the scanner's ownership cost, the other process steps tied to that exposure, and the share of the mask. The prices, derating, process cost and mask figures are illustrative assumptions, not data from ASML, any fab or any mask shop.

Input	Low-NA	High-NA	Basis
Tool price	€220m	€380m	Illustrative. See the note below
Yearly ownership cost: price over 5 years, plus 8% of price for service and running costs	€61.6m	€106.4m	Illustrative
Vendor throughput	220 wph	175 wph	ASML figures for NXE:3800E and EXE:5200B
Throughput used, at 80% of vendor figure	176 wph	140 wph	Illustrative derating
Productive share of the year	85%, or 7,446 hours	80%, or 7,008 hours	High-NA anchored to ASML's "over 80 percent" availability. Low-NA is illustrative
Wafer passes per year	1,310,496	981,120	Calculated
Other process cost per exposure: track, etch, deposition, clean, metrology	€60	€60	Illustrative
Mask price	€200,000	€400,000	Illustrative
Wafers per mask over its life	50,000	50,000	Illustrative

A note on price. ASML does not publish a high-NA list price in the documents used here. Its 2025 EUV sales of €11.6 billion from 48 systems, including high-NA, work out to about €242m per system, which gives a rough sense of scale for the low-NA figure. A trade report from April 2024 put the high-NA tool at about US$380m or more, against about US$180m for the previous generation. Treat that as an unconfirmed market figure, and replace our €380m with your own quote.

A note on throughput. Raw wafer-per-hour numbers are not like for like. ASML's product pages quote a reference dose of 50 mJ/cm² for EXE:5200B and 30 mJ/cm² for NXE:3800E. Planning figures also move: a 2023 ASML roadmap slide showed 220 wph for EXE:5200B, while the 2025 Annual Report gives 175 wph for the shipped tool, and ASML now reports a record 230 wph on NXE:3800E. Always note which figure a cost model is using.

The base result

First, the scanner on its own. Low-NA costs €61.6m divided by 1,310,496 passes, or about €47.0 per pass. High-NA costs €106.4m divided by 981,120 passes, or about €108.4 per pass. That is about 2.3 times as much. If you stop here, high-NA loses to two passes (€94) and wins only against three (€141).

Now add the other costs. A low-NA exposure comes to 47.0 + 60 + 4 = €111.0. A high-NA exposure comes to 108.4 + 60 + 8 = €176.4.

Route for one layer	Cost per wafer (illustrative)	Against high-NA
High-NA, one exposure	€176.4
Low-NA, two exposures	€222.0	€45.6 more
Low-NA, three exposures	€333.0	€156.6 more
Low-NA, four exposures	€444.0	€267.6 more

The €60 line changes the whole argument, so test it first. Cut it to €25 and the layer costs become €141.4 and €152.0, and the two-exposure margin drops to about €11. A self-aligned low-NA flow pushes the other way, because it adds deposition and etch steps of its own. Ask your process team for this number before arguing about scanner prices.

Throughput is the crossover

With everything else fixed, solve for the high-NA throughput at which the two routes cost the same. Against two exposures, high-NA can spend 222.0 less 68 on its scanner pass, which is €154. So €106.4m divided by (154 x 7,008 hours) gives about 99 wph. Against three exposures, the allowance is €265 and the break-even is about 57 wph. Against four, it is about 40 wph.

Our working figure is 140 wph, so there is headroom. At 100 wph the layer costs €219.8, about €2 under two low-NA exposures, which is effectively a tie.

Dose is the main thing that eats this headroom. Exposure time grows with dose, and the required dose depends on the layer and the resist. imec reports about a 60% dose-to-size gain over 0.33 NA for 29 nm pitch holes and pillars, while an ASML slide from 2023 shows a smaller gain of about 9% (63.0 to 57.5 mJ/cm²) on a different structure and test tool. Neither result should be applied to a line and space layer without checking. The published 175 wph holds only at its reference dose, so read your own wafer data if you have it.

Low-NA is also a moving target. ASML says NXE:3800F has a 260 wph specification, with first shipments in 2027 and full volume in 2028. Apply the same 80% derating and the same price, which is our assumption, and a low-NA pass falls to about €39.8. Two exposures then cost about €208, and the high-NA break-even rises to about 109 wph. High-NA productivity will not stand still either, so compare tools available in the same year.

The mask is where the die size bites

High-NA keeps the 6-inch mask format and uses anamorphic optics, with 4x reduction across the slit and 8x in the scan direction. The price is a smaller field: 26 x 16.5 mm against 26 x 33 mm, or 429 mm² against 858 mm². ASML says this means twice as many exposures per wafer, and it has made the stages faster to compensate. Its 2023 presentation cites about 4x higher mask stage acceleration and about 2x at the wafer.

A die that fits within the half field needs one mask per layer. A larger die needs two, stitched together. For AI accelerators and other large devices this is a direct cost, and it also carries engineering risk. ASML's 2023 presentation reports increased CD variation at the stitch, with evaluation continuing at that time. In April 2024, Intel's Mark Phillips was reported as saying that designers cannot treat stitching as fully invisible.

Mask technology adds its own risk. The same ASML presentation says low-n masks, which help imaging, show about 2x to 3x higher sensitivity to mask-making errors. That is why our high-NA mask carries double the price, though the real ratio is for your mask supplier to state.

Here is how the result moves. For the stitched cases we assume two masks per layer and 20% lower throughput, or 112 wph, for the reticle changes. That penalty is an illustrative assumption.

Case (all illustrative)	High-NA	Low-NA x 2	Low-NA x 3	Cheapest route
Base: fits half field, 50,000 wafers per mask	€176.4	€222.0	€333.0	High-NA
Stitched die, 50,000 wafers per mask	€211.6	€222.0	€333.0	High-NA, by about €10
Fits half field, 5,000 wafers per mask	€248.4	€294.0	€441.0	High-NA
Stitched die, 5,000 wafers per mask	€355.6	€294.0	€441.0	Low-NA x 2, unless the layer truly needs three

The last row is the one to remember. A large die at low volume pays for two costly masks across few wafers, so a two-exposure layer is better left on low-NA, while a three-exposure layer still favours high-NA by about €85. If this is your product, also compare it with splitting the large die into chiplets, which changes both the field problem and the yield sum.

What the sum leaves out

Yield. ASML argues that fewer exposures reduce defect risk and shorten cycle time, and this is the main claim the model does not capture. A rough scale helps. Suppose a finished wafer is worth €15,000. Moving five layers from two low-NA exposures to one high-NA exposure saves 5 x €45.6 = €228 in our base case, or about 1.5% of the wafer. On a single layer, a 0.2% yield change is worth €30, which is about two thirds of that layer's saving. So if single exposure yields better, it can matter as much as the cost saving. If depth of focus or stitching makes it yield worse, the saving can disappear. imec expects depth of focus to be 2 to 3 times smaller than at 0.33 NA, which is a real constraint on wafer flatness and resist thickness.

Cycle time and capacity. Fewer steps shorten the time a wafer spends in the fab, and ASML also says the platform needs fewer systems overall on the layers concerned. Whether that matters depends on your backlog, and we have not priced it.

Carbon. imec's model found about a 30% cut in CO2 emissions when one low-NA LELE via module is replaced with a single high-NA exposure, even though the 0.55 NA tool uses more power per step. The study assumed 220 wph for both cases, so results at lower throughput need rerunning.

Competing budgets. High-NA does not arrive alone. At the same nodes, process teams are also paying for new transistors and for backside power delivery, so the layer saving has to be weighed against the total node cost.

Memory. DRAM has a different mix: repeated array patterns usually fit the field, and volumes spread mask costs thinly, so the stitched rows matter less. It is also a market where supply is already tight. Our model does not include the value of extra output, which would come on top of the cost per layer.

How to run this on your own layer

1. Count real exposures. Write down how many low-NA exposures the layer needs at your actual pitch and tip-to-tip rules, not the node's headline number.
2. Get the non-scanner cost per pass. Include self-aligned steps, as well as any added metrology and rework.
3. Check the die against 429 mm². If the die is larger, double the masks and apply a throughput penalty.
4. Divide mask cost by realistic wafers per mask. Include respins and pilot runs.
5. Use throughput at your layer's dose. Do not use the headline figure.
6. Solve for break-even wph. Compare it with what your tool is delivering, not its specification.
7. Add a yield line last. Show the result with and without it, so the decision is clear about how much depends on an assumption.

Our reading is that three-exposure and four-exposure layers carry a wide margin across every case above, while two-exposure layers sit close to the line and depend on die size and volume. Foundry customers will not choose a scanner, but they do choose die size and volume, so this is worth raising before a floorplan is fixed. Our SoC lifecycle on The Semiconductor Hub shows where those decisions fall in a programme.

Sources

• ASML, 2025 Annual Report, strategic report section, 2026 (EXE:5200B throughput, EXE platform statements).
• ASML, transcript of the Q1 2026 investor call, 15 April 2026 (three or four exposures, factor of 10, wafers processed, availability, NXE:3800F).
• ASML, transcript of the Q4 2025 investor call, 28 January 2026 (EUV sales and system count, Intel acceptance).
• ASML, Annual General Meeting presentation, 22 April 2026 (systems shipped, 230 wph on NXE:3800E, insertion timing).
• ASML, product pages for TWINSCAN EXE:5200B and NXE:3800E, read 7 November 2026 (reference doses).
• ASML, news story on high-NA EUV, 25 January 2024 (half-size fields, twice as many exposures).
• van Schoot et al., "The High NA EUV exposure tool: Nearing completion and next steps", EUVL Workshop, June 2023 (field, stage acceleration, stitching, low-n masks, MET5 dose data, roadmap).
• imec, "The case for High NA EUV: unlocking the next era of chip manufacturing", 26 February 2026.
• imec, "Entering the High NA EUV lithography era", 12 July 2024 (depth of focus, CO2 model).
• imec, "High-NA EUV lithography: the next step after EUVL", 4 October 2021 (anamorphic optics, two masks for large dies).
• SK hynix, "SK hynix Introduces Industry's First Commercial High NA EUV", 3 September 2025.
• Peter Clarke, "Intel Fellow discusses high-NA EUV lithography progress", eeNews Europe, 19 April 2024 (trade report: stitching remark and unconfirmed tool price).

The worked example uses illustrative numbers and is not a quote or cost from any supplier. Vendor and company figures are their own claims and targets, as published on the dates shown.