The Break-Even Maths of Building Your Own AI Accelerator

Google, Amazon, Meta and Microsoft all run their own AI accelerators now, and each publishes figures showing that its chip beats a GPU on cost or efficiency for its own work. It is easy to read that as proof that any large buyer should do the same. Those figures say nothing about what the programme cost or how many chips it took to pay that back.

So this post builds the missing sum. It sets a merchant GPU against a custom part using fixed cost, unit cost, software quality and schedule, and adds the routes in between: design partners such as Broadcom and Marvell, licensed subsystems, and renting another company's custom chip. The model's numbers are illustrative, so replace them with your own.

Key takeaways

• Break-even volume is fixed programme cost divided by the saving per unit of useful work, and that saving depends on software as much as on silicon.
• In our illustrative model, a partner-built chip pays back at about 70,600 GPU-equivalents per generation. The same programme needs 600,000 if software delivers 0.6 of a GPU's useful work instead of 0.8.
• A 12-month slip hurts twice, because the merchant part keeps improving while your team keeps being paid. In the model it moves break-even from about 70,600 to about 330,400.
• A design partner lowers the fixed cost and raises the unit price, so it suits the middle of the volume range.
• Published savings are vendors' own claims on their own workloads, so treat them as signals, not inputs.

What the builders actually disclose

Programme	Disclosed partner or route	The company's own claim	What the claim leaves out
Google TPU	In-house project started in 2013. Partner not named in the papers we read	First TPU: about 15 to 30 times faster and 30 to 80 times better TOPS per watt than a contemporary CPU or GPU on Google's inference work	Compared with 2015-era parts. Google calls its TCO confidential
Amazon Trainium	Annapurna Labs, bought in 2015	Trainium2: about 30% better price-performance than comparable GPUs. Chips run rate above $25 billion a year	The run rate also covers Graviton and Nitro
Meta MTIA	Co-developed with Broadcom, which supplies design, packaging and networking. The deal includes more than 1 GW	MTIA 2i: average 44% lower TCO than GPUs on the models launched on it	Models it does not support stay on GPUs
Microsoft Maia 200	TSMC 3 nm. No design partner named in the posts we read	30% better performance per dollar than the latest hardware in Microsoft's fleet	A comparison with its own fleet, with no independent benchmark

None of these companies publishes its programme cost, so the key input to a break-even sum is missing from the public record. We left out unconfirmed market reports on share and unit volumes.

Broadcom reported AI semiconductor revenue of $16.7 billion for its third quarter of fiscal 2026, a figure that includes networking as well as custom accelerators. NVIDIA's latest annual report lists large cloud companies with internal chip teams among its competitors.

The model in two lines

Compare the two routes per unit of useful work rather than per chip. Call that unit a GPU-equivalent: the work one merchant GPU delivers on your target workload.

• Saving per GPU-equivalent = M minus (C divided by p)
• Break-even volume = F divided by the saving

M is the lifetime cost of a merchant GPU. C is the lifetime cost of your chip. p is your chip's delivered performance against that GPU, measured on production models after porting. F is everything you spend before the first chip earns anything, counted per generation.

Lifetime cost matters because purchase price misleads. Google's TPUv4i paper says the company designs for performance per TCO, and reports that TCO tracks system power closely across its TPUs.

A worked example

Every number below is an illustrative assumption. None comes from a vendor, a contract or any company's accounts. Servers, networking and buildings are assumed equal across routes and left out. Volumes are per chip generation.

Illustrative item	Merchant GPU	Design partner	Direct to foundry
Hardware NRE you pay	$0	$150M	$500M
Software: 300 engineers at $400,000 for 3 years	$0	$360M	$360M
Boards, racks and validation	$0	$90M	$90M
Fixed cost F	$0	$600M	$950M
Price per chip	$25,000	$14,000	$11,000
Power per chip	1.5 kW	1.0 kW	1.0 kW
Power and cooling at $1,000 per kW per year, for 4 years	$6,000	$4,000	$4,000
Lifetime cost per chip	$31,000	$18,000	$15,000
Delivered performance p	1.0	0.8	0.8
Cost per GPU-equivalent	$31,000	$22,500	$18,750
Saving per GPU-equivalent		$8,500	$12,250
Break-even, in GPU-equivalents		70,589	77,552

The partner route breaks even at $600M divided by $8,500. Volumes round up. At p of 0.8 that takes 88,237 of your chips, because each delivers 0.8 of a GPU-equivalent.

The two custom routes cross where the extra $350M of fixed cost is repaid by the $3,750 lower cost per GPU-equivalent, which is at 93,334 units. So this example gives three bands:

• Below about 70,600 GPU-equivalents per generation, buy merchant.
• From about 70,600 to about 93,300, use a design partner.
• Above about 93,300, going direct costs least.

In spending terms, 70,589 GPUs at $25,000 is about $1.76 billion. Over a two-year generation that is roughly $0.88 billion a year of merchant purchases on the workload the chip can actually serve. A buyer spending far more in total may still have too little on any one stable workload.

Two cross-checks help. Geoff Tate, in Semiconductor Engineering in March 2025, estimated an accelerator programme's all-in cost at a third to a half of a billion dollars once architecture and software teams are counted. Our partner case sits a little above that. Brian Bailey, in the same publication in October 2023, argued that headline design-cost figures overstate what teams pay, as chips rarely start from nothing. So your F depends heavily on what you can reuse.

NVIDIA reported a 75.0% GAAP gross margin for the second quarter of fiscal 2027. Applied crudely to our $25,000 part, that suggests $6,250 of product cost, but you cannot capture the other $18,750. The figure is company-wide and no guide to any single part, margin funds research and software you would now pay for yourself, and a smaller buyer pays more for wafers, memory and packaging. Hence our direct price of $11,000.

What moves the answer

Here is the partner route, changing one illustrative assumption at a time.

Case	Saving per GPU-equivalent	Fixed cost	Break-even
Base case, p = 0.8	$8,500	$600M	70,589
Better software, p = 0.9	$11,000	$600M	54,546
Weaker software, p = 0.7	$5,285.71	$600M	113,514
Poor software, p = 0.6	$1,000	$600M	600,000
One respin adds $100M	$8,500	$700M	82,353
Merchant vendor cuts its price 20% to $20,000	$3,500	$600M	171,429
12-month slip: merchant cost of work falls 20% to $24,800, and $160M more team cost	$2,300	$760M	330,435

A respin, painful as it is, is the mildest case here, and moves the answer less than a modest shortfall in delivered performance. In this example the saving reaches zero at p of about 0.58, which is $18,000 divided by $31,000. Below that, no volume pays back.

For scale, take a 1 GW site with half its power going to accelerators, also illustrative. At 1.25 kW per GPU-equivalent, 500 MW supports 400,000 GPU-equivalents, about 5.7 times our base break-even. The partner route then nets $2.8 billion ($3.4 billion of savings less $600M) against a $12.4 billion merchant bill. That shows why gigawatt commitments change the conversation, but not the economics of any real deal.

Software is the largest swing factor

The best public evidence comes from Meta's ISCA 2025 paper. One important ranking model started at 50% of the GPU baseline on performance per TCO and reached 180% by launch, with about eight months between first test and production. The chip did not change in that time. Model and software work closed the gap. Meta also reports that its many small and medium models cannot be tuned by hand, and calls this an ongoing challenge.

Google's TPUv4i paper makes a related point. Over 20 months of MLPerf Training results, compiler work improved NVIDIA GPUs by 1.8 times and TPUs by 2.2 times. So the part you buy keeps improving after delivery, and your compiler team has to keep pace. NVIDIA's annual report counts over 7.5 million developers using CUDA and its other tools. An internal chip can do without that community if a few models fill the fleet, but it must replace what you were getting from it.

Framework support lowers the entry cost. Meta says its stack needs no MTIA-specific rewrites to enable models, and Amazon says TorchNeuron runs existing PyTorch code on Trainium unchanged. Treat these as claims about getting a model to run. Reaching the p your business case assumes is a larger task, as Meta's eight months suggest.

The model can also price that work. Suppose doubling the software budget to $720M lifts p from 0.8 to 0.9, again illustratively. The partner route then costs $960M plus $20,000 per unit, against $600M plus $22,500. The extra $360M pays back above 144,000 GPU-equivalents.

Time to market is a cost line

The first TPU is the famous fast case: designed, verified, built and deployed in 15 months, with off-the-shelf GPUs still bought for training. That speed had a price. The paper says the schedule ruled out many energy-saving features, and its authors estimate that a version with more time and GDDR5 memory could have been far better. Scope was also narrow: inference only, on workloads Google controlled.

The target has moved since then. NVIDIA's annual report says it now aims to complete new data centre solutions every year. Google reports its production models growing about 1.5 times a year in memory and compute. A chip frozen three years before volume has to be right about models that do not yet exist. Meta's approach is to shorten the loop, using reusable chiplets and shared racks to reach a stated cadence of roughly six months per chip, though the later parts in that plan are still scheduled rather than delivered.

So compare your chip against the merchant part on sale when yours reaches volume, not the one on sale today.

The routes in between

Most teams have options short of a fully in-house chip. Here are four.

Design partner. You own the architecture and the software, while the partner brings high-speed IP, physical design, packaging and supply. Marvell's annual report shows how the money can flow: its ASIC model tends to carry lower gross margin and typically includes substantial NRE that customers pay against milestones. It also warns that custom parts may have no other buyer, so demand risk sits with the customer. Broadcom's annual report describes its AI customers as hyperscalers and companies with frontier models, and puts its top five end customers at about 40% of net revenue, so you share its attention with some large accounts. Ask what you own when the contract ends.

Licensed subsystems. Arm's Neoverse CSS supplies a pre-integrated, pre-validated compute subsystem, and Arm says one partner saved over 80 engineering years and another went from idea to Linux on over 100 cores in 13 months. Those are Arm's claims about individual projects. At our illustrative $400,000 a year, 80 engineering years is $32M, or about 3% of the $950M direct route. So the larger benefit is likely schedule and lower risk, and the subsystem covers the host side of the chip, not the accelerator's compute fabric or compiler.

Mixing with the merchant platform. NVIDIA's annual report describes NVLink Fusion, which lets hyperscalers and custom ASIC designers attach their own CPUs and XPUs to its platform. This can reduce networking risk, at the price of closer dependence on that vendor.

Renting someone else's custom chip. Here F is close to zero, apart from porting. Alphabet says TPU systems sales made a meaningful contribution to Google Cloud's growth in the third quarter of 2026, and Amazon says it intends to offer Trainium outside AWS in late 2027. A buyer below break-even may get much of the benefit without a chip team, though the supplier keeps the roadmap and part of the margin.

Five questions before you commit

1. How much stable volume is there per generation? Count only models the chip will really serve. Meta's paper is candid that unsupported models stay on GPUs.
2. Do you control the software that runs on it? Internal workloads let you co-design models.
3. What p have you measured? Use production models, and test the case where p comes in 0.1 to 0.2 below plan.
4. Can you fund more than one generation? Reuse across generations is where F falls, so model the second chip before approving the first.
5. Do you have secured supply? Your chip competes for the same memory and packaging as everyone else's. See our post on the AI memory squeeze.

The model leaves things out. It ignores the time value of money, so early spending looks cheaper than it is. It gives no credit for supply security, which Meta names as a motive. It also ignores fleet health, which becomes your problem alone: Meta's paper describes using firmware updates to work around silicon defects, and our post on silent data corruption covers why that matters at scale. For background, see our history of tensor processing units. Our SoC lifecycle on The Semiconductor Hub shows where these commitments fall in a programme.

Sources

• Jouppi et al. (Google), "In-Datacenter Performance Analysis of a Tensor Processing Unit", arXiv:1704.04760, April 2017, ISCA 2017.
• Jouppi et al. (Google), "Ten Lessons From Three Generations Shaped Google's TPUv4i", ISCA 2021.
• Coburn et al. (Meta), "Meta's Second Generation AI Chip: Model-Chip Co-Design and Productionization Experiences", ISCA 2025.
• Meta, "Four MTIA Chips in Two Years", 11 March 2026, and "Meta Partners With Broadcom to Co-Develop Custom AI Silicon", 14 April 2026.
• Amazon, pages on the Q1 2026 and Q3 2026 earnings calls and "How Amazon became one of the world's top chip companies in a decade", aboutamazon.com, undated.
• Microsoft, "Maia 200: The AI accelerator built for inference", 26 January 2026.
• NVIDIA, Form 10-K for the fiscal year ended 25 January 2026, and "NVIDIA Announces Financial Results for Second Quarter Fiscal 2027", 26 August 2026.
• Broadcom, Form 10-K for fiscal 2025, filed 18 December 2025, and third quarter fiscal 2026 results, 2 September 2026.
• Marvell, Form 10-K for the fiscal year ended 31 January 2026, filed 11 March 2026.
• Alphabet, third quarter 2026 earnings release, 28 October 2026.
• Arm, "Driving the Custom Silicon Revolution with Arm Neoverse Compute Subsystems", 28 August 2023.
• Geoff Tate, "GPU Or ASIC For LLM Scale-Up?", Semiconductor Engineering, 17 March 2025.
• Brian Bailey, "What Will That Chip Cost?", Semiconductor Engineering, 30 October 2023.

The worked example uses illustrative numbers, not data from any company. Vendor figures are the companies' own claims, as published on the dates shown. This is engineering and business analysis and is not investment advice.