Verilog
Verilog Interview Questions: Display Values, Delays and Clock Dividers
Q: Given the following Verilog code, what value of "a" is "displayed"? always @(clk) begin a = 0; a <= 1; $display(a); end Q: Given the following snippet of Verilog code, draw out the waveforms for "clk" and "a". always @(clk) begin a = 0; #5 a = 1; end Q: What is the difference between the following two lines of Verilog code? #5 a = b; a = #5 b; Q: Write Verilog to provide a d…