Showing posts from February, 2005
Archive: February 2005
Interview Questions
A delay locked loop (DLL) is a clock circuit that adds an adjustable delay to an incoming clock so that the clock arriving at the registers lines up with the input clock edge. Unlike a phase locked loop (PLL), it has no oscillator: it delays the existing clock instead of generating a new one, which gives it low jitter accumulation and simple, stable loop behaviour. DLLs are used for clock deskew in FPGAs, in DDR memory interfaces and in high-spe…
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The Editor's Desk
February 28, 2005
Tutorials
PLL stands for 'Phase-Locked Loop' and is basically a closed loop frequency control system, whose functioning is based on the phase sensitive detection of phase difference between the input and output signals of the controlled oscillator (CO). For further info, click on the title...
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The Editor's Desk
February 28, 2005
RTL Design
Check out the FIFO Depth Calculator here: https://blog.digitalelectronics.co.in/p/fifo-depth-calculator.html FIFO depth is the number of entries a buffer needs so that a burst from a fast or bursty writer never overflows while a slower or less frequent reader drains it. The basic method is simple: work out how long the write burst lasts, count how many items the reader can remove in that same time, and the difference is the minimum depth. On t…
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The Editor's Desk
February 28, 2005
Tutorials
Advanced Microcontroller Bus Architecture (AMBA): Description: The AMBA™ on-chip interconnect system is an established open specification that details a strategy on the interconnection and management of functional blocks that makes up a System-on-Chip (SoC). It is a high-speed, high-bandwidth bus that supports multi-master bus management to maximize system performance. AHB serves the need for high-performance SoC as well as aligning with current…
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The Editor's Desk
February 27, 2005
Tutorials
SOC interconnect bus: These buses are used within a chip to interconnect an different IP cores to the surrounding interface and peripheral logic. Some buses... Atlantic Interface , Avalon Bus Specification -- Altera corp. WISHBONE -- Opencores.org. AMBA , AHB (Advanced High-performance Bus) , APB (Advanced Peripheral Bus), ASB(Advanced System Bus) -- ARM. CoreConnect Bus -- IBM. Open Core Protocol 'OCP' -- Open Core Protocol Internat…
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The Editor's Desk
February 27, 2005
Tutorials
The Inter-IC bus, commonly known as the I²C ("eye-squared-see") bus, is a control bus that provides the communications link between integrated circuits in a system. Developed by Philips in the early 1980s, this simple two-wire bus with a software-defined protocol has evolved to become the de facto worldwide standard for system control, finding its way into everything from temperature sensors and voltage level translators to EEPROMs, ge…
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The Editor's Desk
February 26, 2005
Tutorials
HDLC (High-level Data Link Control) is a bit-oriented data link layer protocol, standardised by ISO, that carries data in frames marked by the flag pattern 01111110 (0x7E). Each frame holds an address, a control field, optional data and a CRC frame check sequence, and bit stuffing keeps the flag pattern from appearing inside the frame. HDLC and its variants are the basis of LAPB (X.25), LAPD (ISDN), Frame Relay framing and PPP framing. Key tak…
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The Editor's Desk
February 26, 2005
Tutorials
There are two main types of timing verification: dynamic timing, where the design is simulated with real delays and a set of test vectors, and static timing analysis (STA), where the tool adds up the delays along every path and compares them with the clock without any vectors. STA is fast and complete for synchronous logic, so it is the sign-off method for most digital chips. Dynamic timing simulation is slower and only as good as its vectors, b…
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The Editor's Desk
February 26, 2005
Tutorials
Intrinsic device delay: Time taken for the cell to change state due to a change on the input pins. Interconnect delay: Delay due to wires. Dependent on layout. Smaller dimensions means more resistance. Making the wires "taller" leads to more capacitance. • The total delay is the sum of the gate delay and the interconnect delay. Delay is mostly determined by the layout (placement) but varies with temperature, voltage and process. • At a…
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The Editor's Desk
February 26, 2005
Static Timing Analysis
Clock skew is the difference in arrival time of the same clock edge at two different registers. A short path is a register-to-register data path so fast that, when the capture clock arrives late, new data races through and overwrites the value the capture flop should still be holding. That race is a hold-time violation, and unlike a setup violation it cannot be fixed by slowing the clock. The cure is to measure skew with static timing analysis a…
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The Editor's Desk
February 26, 2005
Verilog
These are questions from an Intel interview for a CMOS circuit and VLSI design role, collected in 2005, with answers. They span computer architecture (buses, pipelines, caches and coherence), digital design (state machines and synchronisers), CMOS device and circuit basics (MOSFET curves, inverters, delay, power), interconnect, SRAM design and test. The mix is typical of circuit design interviews at large processor companies: fundamentals first,…
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The Editor's Desk
February 25, 2005
