Why not a PLL:
PLLs have disadvantages that make their use in high-speed designs problematic, particularly when both high performance and high reliability are required. The PLL voltage-controlled oscillator (VCO) is the greatest source of problems. Variations in temperature, supply voltage, and manufacturing process affect the stability and operating performance of PLLs.
DLLs, however, are immune to these problems. A DLL in its simplest form inserts a variable delay line between the external clock and the internal clock. The clock tree distributes the clock to all registers and then back to the feedback pin of the DLL. The control circuit of the DLL adjusts the delays so that the rising edges of the feedback clock align with the input clock. Once the edges of the clocks are aligned, the DLL is locked, and both the input buffer delay and the clock skew are reduced to zero.
Advantages:
PLLs have disadvantages that make their use in high-speed designs problematic, particularly when both high performance and high reliability are required. The PLL voltage-controlled oscillator (VCO) is the greatest source of problems. Variations in temperature, supply voltage, and manufacturing process affect the stability and operating performance of PLLs.
DLLs, however, are immune to these problems. A DLL in its simplest form inserts a variable delay line between the external clock and the internal clock. The clock tree distributes the clock to all registers and then back to the feedback pin of the DLL. The control circuit of the DLL adjusts the delays so that the rising edges of the feedback clock align with the input clock. Once the edges of the clocks are aligned, the DLL is locked, and both the input buffer delay and the clock skew are reduced to zero.
Advantages:
- precision
- stability
- power management
- noise sensitivity
- jitter performance.
Hello there, and thank you.
ReplyDeleteI work for a small start-up and for now i will keep it a secret ;-). I do have a Masters in EE specializing in ASIC & DSP. BTW i m a native of TN, INDIA.
Hi, Sorry i don't have much info on that. I will see if i can get that info from my friends.
ReplyDeleteHi I want to do a project on delay locked loop for my masters degree, can anyone suggest me some good IEEE papers on DLL and some good materials
ReplyDeleteHi all,
ReplyDeleteI am a student, would like to design a Delay locked loop. Is Pspice able to help me in the simulation ?
1) Is Pspice suitable for a timing simulation?
2)Pspice can change the (process , voltage, temperature )PVT in the setting?
3) Does Pspice can add additional libraries in the tools?
or any simulation tools that able help me?
thanks .
helps in need...
warmest regards;
danes