800 V DC for AI Racks: Six Failure Modes Chip Teams Must Design For

Moving a 1 MW rack from 54 V to 800 V cuts the current from about 18,500 A to 1,250 A, and that sum explains why the industry is making the change. It also creates a different kind of fault problem: a low-impedance DC network full of capacitors, with no current zero crossing to help extinguish an arc, and protection that may need to act within microseconds.

Most writing on this subject is aimed at facility engineers. This review takes the same failures and asks what each one demands of the silicon in breakers, converters, sensors and controllers. It is an engineering discussion only, and it is not legal, compliance or electrical safety advice.

Key takeaways

• In the first moments of a short circuit, the capacitors on the bus can matter more than the source. Limiting the source alone does not stop them discharging into the fault.
• Clearing time sets how much local energy storage healthy loads need. In our illustrative sum, going from 20 ms to 0.5 ms cuts the capacitance for a 1 MW load from about 329 mF to about 8 mF.
• A series arc may draw too little current to trip overcurrent protection, so it needs its own sensing, and that sensing has to work beside noisy converters.
• A first ground fault in a high-resistance grounded system does not stop the load, which makes it easy to leave unrepaired. Monitoring parts therefore carry real safety weight.
• Short-circuit figures for GaN and SiC devices depend heavily on test voltage and on whether the stress is repeated. A single-pulse number from a 400 V or 600 V test says little about an 800 V bus.

The system is still being defined

"800 V" does not yet describe one system. NVIDIA's white paper "800 VDC Architecture: Industry Alignment & Execution" lists four grounding approaches under evaluation: high-resistance midpoint, high-resistance return, floating and solid. The OCP Mt. Diablo specification, version 1.0.0, allows both resistive and solid grounding, for ±400 V or differential 800 V outputs. NVIDIA's paper says transient limits and stability criteria are still being worked through, and that 800 V DC is meant to coexist with AC.

A part specified today has to state its assumptions. Here is where silicon sits in the published designs:

Layer	Published detail	Silicon involved
Source	Power rack of about 660 kW initially, or an end-of-row power centre of up to 2 MW using SiC power shelves or IGBT rectifiers (NVIDIA)	Power stages, controllers, current limit circuits
Branch protection	125 A tap cans. Moulded-case breakers are expected in initial production, with clearing of up to about 20 ms. NVIDIA is targeting solid-state breakers at 125 A and 1,250 A	SiC switches, gate drivers, fast current sensing
Rack conversion	800 V to 54 V shelves using 15 kW supplies today, with native 800 V racks planned	GaN or SiC stages, isolated drivers, digital control
Monitoring	Insulation monitoring, residual current monitoring, connector temperature, high-frequency arc sensing	Precision analogue front ends, isolators, signal processing

Below the rack, the same current problem carries on into the package, which we looked at in Backside Power Delivery.

Failure 1: the capacitors dump first

The Siemens and NVIDIA paper "Protections for Data Centers Powered by Direct Current" simulates a floating 800 V, 1 MW block with one source and four loads, then shorts one load. With fuses, melting takes about 1 ms. The capacitors of the three healthy loads discharge into the fault through the shared bus, and recovery takes about 20 ms. With a solid-state breaker set to trip at twice nominal current after a 3 µs delay, peak current stays under 800 A and the healthy loads see about 1 V of variation.

The same paper reports that only the solid-state breaker could interrupt a capacitor discharge rising at 200 A/µs. It gives hybrid breakers 1 to 3 ms and solid-state breakers under 0.5 ms.

Here is what that means for a breaker chip set. These numbers are illustrative, not product data.

• Detection delay. At 200 A/µs, each microsecond of delay adds 200 A, so 3 µs adds 600 A to the current the switch must turn off.
• Loop inductance. With 800 V across the loop, 200 A/µs implies 800 / 200 = 4 µH. At 800 A, that inductance holds 0.5 × 4 µH × 800² = 1.28 J, which the clamp has to absorb at a voltage above the bus.
• On-state heat. At 125 A and 5 mΩ, conduction loss is 78 W. At 1,250 A and 1 mΩ, it is about 1.56 kW. NVIDIA describes its 1,250 A breaker as likely liquid cooled.

Our reading is that the sense path, comparator and gate driver should share one timing budget that holds across temperature and noise.

A worked example: what slow clearing costs

While a fault is being cleared, healthy loads have to live on local storage. Every number is an illustrative assumption. It takes a 1 MW constant-power load, a droop from 800 V to 720 V, and no losses. The formula is C = 2Pt / (V1² - V2²), where V1² - V2² is 121,600 V².

Clearing time	Capacitance	Stored at 800 V
20 ms (upper figure NVIDIA gives for a 125 A moulded-case breaker)	329 mF	105 kJ
10 ms	164 mF	53 kJ
1 ms	16.4 mF	5.3 kJ
0.5 ms (upper figure Siemens gives for a solid-state breaker)	8.2 mF	2.6 kJ

The Siemens paper gives roughly 80 mF for 10 ms at 1 MW within 10%. Our figure is about twice that because we start the droop at 800 V. A swing from 880 V to 720 V gives about 78 mF, which may be their assumption, though the paper does not spell it out.

There is a catch in the last column. That stored energy can feed the fault unless it is blocked. Siemens relies on reverse-blocking diodes for this, and warns that storage on the main bus both supports healthy loads and contributes to the fault. For a chip team, the delay of the protection path is therefore a system cost as well as a datasheet line.

Failure 2: the slow fault nobody sees

Low-level faults can be harder than bolted ones. In a Siemens case study, a branch at twice nominal current on a converter feeding four loads looks like only 1.25 times nominal to the converter, so the converter carries on normally, and clearing with fuses or mechanical breakers can take minutes.

Series arcs are the sharpest version of this. NVIDIA's paper states that they generally do not produce enough overcurrent to operate conventional protection, and calls for electrical signature analysis, thermal monitoring or similar sensing. The hard part for silicon, in our view, is telling an arc's signature from the switching noise of nearby converters. Ask any sensor supplier for detection and false-alarm rates measured on a real converter load.

Prevention sits in the connector. NVIDIA's 125 A whip uses a mechanical lock and a normally open contactor, so power is removed before the connector unlocks. Mt. Diablo asks for short sense pins and a latch that cannot release until power is off.

Failure 3: the ground fault that does not stop anything

High-resistance grounding keeps the system running through a first ground fault. The appendix to Mt. Diablo sets out the downside plainly: because the first fault does not disrupt operation, it may get low priority, and a second fault can create a fire or shock risk. It also warns that defective sensors can give a false sense of security.

Three points follow for chip designers:

1. Self-test. Monitoring parts need a way to prove they still work in the field.
2. Grounding assumptions. Mt. Diablo warns that a component designed for a high-impedance scheme may lack input fuses, or may use only functional insulation to chassis, which may not suit a low-impedance system. Spacing and isolation choices should be written against a named scheme.
3. Timing. The Siemens paper describes UL 943C Class E as requiring ground fault interruption in about 850 µs at 400 V and about 300 µs at 800 V, which it says existing interrupters cannot achieve.

Failure 4: the charge that stays after off

An electronic fuse has no air gap. The Siemens paper says that is why it cannot count as branch protection, only as supplementary protection under UL 2367, a standard that it says covers only up to 60 V DC. Off-state leakage can reach tens of milliamps and can keep downstream capacitors charged. UL 489i requires a solid-state breaker in standby to discharge capacitors or carry a warning.

As an illustrative sum, 10 mA into 10 mF reaches 800 V in 0.01 × 800 / 0.01 = 800 seconds, about 13 minutes, if nothing bleeds that charge away. Vertiv's web summary of its October 2026 white paper says bus capacitance and battery modules can hold dangerous voltage for seconds to minutes after isolation. Leakage at temperature and end of life belongs in the safety case.

Failure 5: the bus that oscillates

A tightly regulated converter behaves as a constant-power load: when input voltage falls, it draws more current. Pizniur, Shan and Jatskevich describe this negative incremental impedance as a known source of oscillation in DC systems, up to a limit set by the converter's control bandwidth. In textbook form, the incremental impedance is minus V²/P, which at 800 V and 1 MW is minus 0.64 Ω.

The load makes this harder. Mt. Diablo lists 175% to 180% of thermal design power for steps under 0.5 to 2 ms, depending on the vendor, and example load profiles up to 10 kHz. At the slow end, Choukse and colleagues at Microsoft, OpenAI and NVIDIA report training traces with energy concentrated between 0.2 and 3 Hz, and swings of tens of megawatts inside one site. The wider power bill of AI is the subject of The Hidden Cost of Agentic AI.

NVIDIA lists frequency-domain stability, source output impedance and a restriction on distribution inductance among the things its simulation work will define. Until those are published, a controller vendor should expose loop parameters and provide an input impedance model. That is our recommendation.

Failure 6: the power device itself

GaN. Ruizhe Zhang's 2023 Virginia Tech dissertation points out that a lateral GaN HEMT has no p-n junction between source and drain, so it lacks an avalanche mechanism. It also finds that breakdown voltage is "dynamic", moving with switching conditions through buffer trapping, so a single-pulse test may not show the real limit.

Short-circuit data shows how test conditions drive the numbers. Zhang reports a 650 V vertical Fin-JFET surviving 30.5 µs at 400 V, 17.0 µs at 600 V and 11.6 µs at 800 V. Yang and colleagues (IEEE Transactions on Power Electronics, July 2026, as reported by Semiconductor Today) claim a record 629 µs at 450 V for a Schottky p-GaN device, falling to 337 µs at 550 V. In the same work, two commercial comparison parts failed at the third repetitive cycle. These are research results on specific devices, and they should not be read across to any product. Supply is a question too, since TSMC is leaving the GaN wafer foundry business.

SiC. Green, Habersat and Lelis at the US Army Research Laboratory (2019) measured 6 to 13 µs on commercial devices at 25 °C, 20 V gate and 600 V drain, with trench parts less robust than planar ones. They found a series of short incremental pulses detected failure better than a single long pulse, including delayed failures. That test voltage is below an 800 V bus, so do not carry the figures over. The same abstract reports a wide spread in threshold stability among commercial devices.

Ball and colleagues at Vanderbilt (2018) treat terrestrial neutrons as a cause of single-event burnout in SiC MOSFETs, so ask for sea-level FIT data at your actual blocking voltage.

A solid-state breaker also has an unusual duty, as we read it: years of conduction, then perhaps one violent event. We would ask for qualification that matches that profile.

A review tool for your spec

This table is our own summary for a design review.

Failure	Silicon that responds	Question to answer
Bolted short, capacitor discharge	Sensor, comparator, driver, switch, clamp	What is the delay from fault to turn-off at worst-case temperature, and what peak current does it allow at your di/dt?
Low-level overcurrent	Current monitor, controller	Who sees a branch fault too small to move the source, and how long may it last?
Series arc	High-frequency front end, signal processing, temperature sense	What are the detection and false-alarm rates on a real converter load?
First ground fault	Insulation and residual current monitors, isolators	Which grounding scheme is assumed, and can the monitor prove it still works?
Trapped charge	Solid-state switch, bleed path	What is off-state leakage at temperature and end of life, and how long until a safe voltage?
Bus instability	Converter controller	Is an input impedance model available, and against what source impedance was stability shown?
Device failure	GaN or SiC stage	Was short-circuit and overvoltage data taken at your bus voltage, with repeated stress?

Our SoC lifecycle on The Semiconductor Hub shows where requirements like these enter a programme, which is well before tape-out.

FAQ

Is 800 V DC more dangerous than AC?

It is different, and a simple ranking is not supported. NVIDIA's comparison says DC arcs are harder to extinguish, while fault energy is often lower in converter-limited systems, and both need strict personnel protection. Schneider Electric's August 2026 study, as reported by TED Magazine, found rack-level incident energy well below the 1.2 cal/cm² reference and centralised cases that depend on protection. That is a vendor study.

Are solid-state breakers the answer to everything?

No. They bring on-state heat and cost, and NVIDIA expects moulded-case breakers to be the main branch device in initial production because of availability and certification.

Sources

• G. Yang (Siemens) and M. Tu (NVIDIA), "Protections for Data Centers Powered by Direct Current", Siemens technical paper, undated, with PDF file metadata of December 2025.
• J. Huntington and M. Tu, "800 VDC Architecture: Industry Alignment & Execution", NVIDIA white paper, 2026.
• Open Compute Project, "Mt. Diablo Disaggregated Power Rack Specification", version 1.0.0, 8 October 2026.
• Choukse et al., "Power Stabilization for AI Training Datacenters", arXiv:2508.14318, August 2025.
• Pizniur, Shan and Jatskevich, "Ensuring Dynamic Stability of Constant Power Loads in Future DC Distribution Power Systems Using Active Damping", 2014.
• R. Zhang, "Robustness of Gallium Nitride Power Devices", Virginia Tech dissertation, September 2023.
• M. Cooke, "GaN HEMT short-circuit performance", Semiconductor Today, September 2026, on Yang et al., IEEE Transactions on Power Electronics, July 2026.
• Green, Habersat and Lelis, "Selected Issues for SiC Mosfet Reliability", 236th ECS Meeting, October 2019.
• Ball et al., "Terrestrial Neutron-Induced Single Event Burnout Cross-Sections and FIT Rates for High-Voltage SiC Power MOSFETs", Geant4 Space Users Workshop, November 2018.
• Vertiv, "800 VDC architecture selection for high-density AI compute", web summary, October 2026.
• "New Schneider Electric study tackles 800 VDC data center risks", TED Magazine, 12 August 2026, on Schneider Electric, "DC Arc Flash Analysis".

The worked examples use illustrative numbers. Vendor figures are the companies' own claims and targets, as published on the dates shown. This post is not legal, compliance or safety advice.