Glass Core Substrates: Promise, Cracks and a Realistic Timeline

Intel put glass core substrates in the headlines in September 2023 and said complete solutions would reach the market in the second half of this decade. More than three years on, a technical note from the IEEE Electronics Packaging Society, updated in November 2025, still says glass has yet to be commercialised. Both statements can be true, and the gap between them is the subject of this post.

Glass solves real problems in large AI packages, but it swaps a warpage problem for a fracture problem, and it moves stress from the die side to the board side. Below we compare the three core materials, look at how through-glass vias are made and how they crack, work through two small examples, and give a dated view of when volume is plausible.

Key takeaways

• Glass offers flatness, stiffness and a tunable expansion coefficient on large panels. Its thermal conductivity is poor, and it is brittle.
• Low expansion is not free. A core matched closely to silicon is badly mismatched to the circuit board, and the industry has not agreed on the best value.
• Suppliers now report fixes for edge cracking, but these are mostly their own results. Board-level reliability data remains thin.
• Schedules have slipped repeatedly. Absolics first aimed for June 2024, and SKC has since said a specific mass production date is hard to forecast.
• Our reading: first qualified low-volume shipments in 2027 or 2028, and high-volume data centre use no earlier than about 2029 or 2030. That is a judgement, not a published fact.

Three cores compared

Silicon usually appears as an interposer above an organic substrate, as our post on silicon interposers explains, while glass is proposed mainly as a replacement for the organic core.

Property	Glass core	Organic core	Silicon
Expansion coefficient	0 to 9 ppm/°C, depending on composition	3 to 17 ppm/°C	About 2.6 ppm/K at 300 K
Young's modulus	50 to 90 GPa	10 to 40 GPa	Rated good for rigidity
Glass transition	Above 600 °C	150 to 200 °C	Not applicable; rated good for temperature resistance
Dielectric behaviour	Dk about 3 to 7; loss varies widely by glass	Dk about 4 to 8; rated good for Dk and loss	High transmission loss
Thermal conductivity	About 1.09 W/(m·K) for one display glass	Rated poor	135 W/(m·K) in one recent thin-die model
Format	Panels; 650 mm by 550 mm via substrates reported	Panels, mature	300 mm wafer only
Vertical connection	Through-glass vias, with pitch under 100 µm by laser drilling	Through holes, which get harder to shrink as the core thickens	Through-silicon vias, usually under 20 µm across
Process maturity	Under development	Mature	Mature

The ranges and ratings come from the Lai review and the IEEE note listed under Sources, whose author works at AGC, a glass supplier. The glass conductivity is from Corning's EAGLE XG sheet, a display product used here only as a representative glass. Values depend on the exact grade.

Electrical

Glass composition matters more than the word "glass" suggests. The IEEE note gives Dk 5.8 and Df 0.006 at 10 GHz for AGC's alkali-free EN-A1, and Dk 3.8 and Df 0.0002 for its synthetic silica AQ. That is a factor of 30 in loss tangent. The note also reports the added insertion loss of a via at 30 GHz as 0.48 dB for conformal plating, 0.34 dB for partial fill and 0.23 dB for full fill, so more copper in the via means lower loss. These are supplier-authored figures.

Two cautions follow. First, the lowest-loss glass is not automatically the best core. In a finite element study by Le, Yoo and Choa, fused silica, with an expansion coefficient of 0.57 ppm/°C, showed the highest crack driving force of the glasses modelled. Second, the core is only one part of the signal path. Build-up layers on glass are still polymer and copper, so in our reading the gain is clearest for the through-core path and for high-frequency designs that use the glass directly, and smaller for a line that stays in the build-up.

Thermal

Glass survives process temperatures that organic resin cannot, and Intel lists this among its reasons for adopting it. But it conducts heat poorly. As an illustration, using 800 µm thickness and the two conductivities in the table, a glass slab has a through-thickness resistance of about 7.3 K·cm²/W before any vias, and the same thickness of silicon about 0.06 K·cm²/W. That is a ratio of about 124. Organic is rated poor as well, so glass loses little by replacing it, but it loses heavily if it replaces a silicon path that was spreading heat. Copper via density and top-side cooling then become part of the thermal design.

Handling

Glass bonds are strong, but practical strength is about two orders of magnitude below the flawless value because surface flaws concentrate stress. The IEEE note points out that bending stress varies inversely with the square of thickness. All else being equal, halving a core from 800 µm to 400 µm makes the same bend four times as severe. Larger panels are also more likely to contain a defect.

How through-glass vias are made

Three laser routes lead the field, according to the IEEE note:

• CO2 laser drilling. It is fast and stable, but thermal stress is unavoidable and has to be managed through pattern design and annealing. The holes are tapered.
• Excimer laser drilling. It causes less thermal damage but is slow, although metal masks can raise throughput. The holes are also tapered.
• Laser modification plus wet etching. An ultra-short pulse laser weakens a track through the glass, and an etch opens it, usually with hydrofluoric acid chemistry. Vias tend to be hourglass shaped.

Metallising the hole is just as hard. Adhesion to smooth glass is weak, so a layer of titanium, chromium or a metal oxide is often added before the copper seed, and filling a tall narrow hole needs better plating additives and solution flow. Intel described 1:20 vias at ECTC 2025. At that ratio an 800 µm core implies a 40 µm hole, which is our arithmetic and not an Intel figure.

A quick check on via density

Illustrative numbers. On a square grid, via count per mm² is (1,000 / pitch in µm) squared. A 250 µm pitch gives 16 vias per mm², and a 100 µm pitch gives 100, which is 6.25 times as many. If Intel's claim of a 10 times increase in interconnect density were read as via density alone, pitch would have to shrink by the square root of 10, about 3.16, so 250 µm would become about 79 µm. Intel's release does not define its claim in those terms, so this is only a sense check.

Where glass cracks

Around the via. Copper expands far more than glass. Taking 17.6 ppm/°C for copper and an illustrative 3.2 ppm/°C for glass, cooling from a 400 °C anneal to 25 °C gives a mismatch of 14.4 ppm/°C over 375 °C, or 0.54% free strain. The Lai review describes radial cracks forming on heating, as copper pushes outward, and circumferential cracks on cooling, as copper tries to pull away. Corning work cited there found no radial cracks at heating rates of 6.5 °C/min or below, and no circumferential cracks in conformally plated vias with copper below 12 µm, in those specific test structures. Modelling also suggests that annular vias have a lower crack driving force than solid ones.

The review is candid about limits. Models disagree on the direction of the aspect ratio effect and on pitch, partly because they use different loads and via types, and most lack direct experimental correlation. So copy rules of thumb with care.

At the diced edge. This is the failure known as SeWaRe, a term coined by Koizumi in 2013 from the Japanese for wood splitting. A horizontal crack grows from a dicing flaw, driven by stress from the mismatch between glass and build-up layers. Fracture toughness varies by only about 10% either way among common glasses, says the IEEE note, so the practical levers are lower stress and smaller flaws. Published fixes include:

• Thinner build-up and better dicing. McCann and colleagues combined these with stronger adhesion and a pullback at the edge, and reported no cracking after 1,000 cycles from minus 40 °C to 125 °C.
• Edge coating. Shinko's release says this suppressed SeWaRe even after a 260 °C reflow test. This is Shinko's own prototype result.
• Edge clearance. In the Le study, a clearance of 300 µm or more kept the crack driving force well below threshold. The same 2D model puts the risk as significant at three redistribution layers and over the threshold at four, under its assumed conditions, and its authors say it has not been validated by experiment.

Reports of Intel's thick-core sample, shown in January 2026 with ten build-up layers per side, say Intel saw no SeWaRe in testing. That is a vendor claim reached through trade reports, but it suggests the model limit above is not a hard wall. High via density has its own cost: a TSMC study from 2011 found that fracture strength falls as via pitch shrinks, measuring 120 to 140 MPa against simulated stresses of 80 to 100 MPa.

A worked example: warpage against board stress

Why not simply match the core to silicon? Every input is an illustrative assumption. It uses plain free-expansion mismatch at the corner of each interface: expansion difference × temperature change × distance from the centre. It ignores modulus, build-up layers, solder creep and underfill, so it shows the direction and not a warpage value.

Assumptions: silicon at 2.6 ppm/°C, over a 60 mm by 60 mm die area, which puts the corner 42.4 mm from the centre, with a 200 °C swing during assembly. The board is at 17 ppm/°C, under a 100 mm by 100 mm package, which puts the corner 70.7 mm from the centre, with a 100 °C swing in use.

Core expansion	Die side mismatch	Die side corner displacement	Board side mismatch	Board side corner displacement
3.2 ppm/°C (low)	0.6 ppm/°C	5.1 µm	13.8 ppm/°C	97.6 µm
8.3 ppm/°C (moderate)	5.7 ppm/°C	48.3 µm	8.7 ppm/°C	61.5 µm
10 ppm/°C (organic-like)	7.4 ppm/°C	62.8 µm	7.0 ppm/°C	49.5 µm

To check one cell: 0.6 × 10⁻⁶ × 200 × 42.4 mm = 0.0051 mm, or 5.1 µm. Going from 10 to 3.2 ppm/°C cuts the die side figure by about 12 times and roughly doubles the board side figure.

This matches the published argument. At ECTC 2025, Unimicron argued for a higher expansion core to protect board-level reliability, and the Lai review says there is still no clear recommendation on glass expansion strategy. It reports a package-level trend that keeps improving as the mismatch falls, and a sweet spot at board level; one simulation there favoured about 8.3 ppm/°C. Our notes on BGA package selection are worth reading alongside this, because the solder joints pay for that board side number.

Real results are far less dramatic than the 12 times here. Shinko, reporting on its own build-up substrate, says warpage came in at less than half that of conventional organic cores, with about 35% less variation in positional accuracy of the outermost alignment mark. Intel's 2023 claim was 50% less pattern distortion. These are vendor numbers, but they are a more sensible gain to plan around.

A dated timeline, and what it supports

Date	Event	Status of the evidence
Sept 2023	Intel says it is on track for complete solutions in the second half of the decade	Company release; a target
Jan 2025	US Commerce awards Absolics $100 million to build a glass-core ecosystem around its low-volume Covington plant. A separate award of up to $75 million is listed for the 120,000 sq ft facility	Government records
ECTC 2025	ECTC panel lists singulation without cracking and high layer counts as unsolved, and board-level reliability as still under study	Conference report by TechSearch
May 2026	SKC discloses that a specific Absolics mass production schedule is hard to forecast, after earlier goals of June 2024, 2025 and certification in 2026	Korean press on a company filing
May 2026	SEMI and Global Net say initial production could begin around 2028 in selected high-performance uses	Market report; scenario average; not independently confirmed
July 2026	Samsung Electro-Mechanics and Dongwoo Fine-Chem agree a glass core venture of about KRW 480 billion, operating from the second half of 2027	Korean press on a company announcement; a plan
July 2026	SKC says embedded product is in reliability evaluation in Taiwan, with results sought this year before a proof of concept	Korean press on the earnings call
Aug 2026	Absolics announces a KRW 401.1 billion rights issue for evaluation, certification and yield, with large expansion dependent on customer results. Samsung Electro-Mechanics reports some customers in technical approval and sample evaluation, and aims for full-scale operation from 2028	Korean press on a filing and an earnings call
Sept 2026	Korean press describes Absolics' embedded product as having started initial reliability testing, with completion planned for the second half	Single press report

We found no Intel announcement naming a product or a volume quarter, and no public confirmation of a qualified high-volume customer anywhere. Our own reading, which is a judgement and not a sourced forecast:

• 2026: no volume. Samples and reliability work only.
• 2027 to 2028: plausible first qualified shipments at low volume, more likely in simpler non-embedded parts or selected high-performance products than in the largest AI packages.
• 2029 to 2030 or later: plausible high-volume data centre use, if board-level data arrives and is good.

By November 2026, Absolics' original date was about 29 months in the past, and the most recent public statements describe testing and not shipment. So we would plan on the later end of each range. Bridge approaches of the kind in our EMIB and CoWoS comparison remain the available route for today's programmes.

What would change this view

1. A named customer announcing a qualified product on glass, instead of an evaluation.
2. Published board-level thermal cycling on a large body, from someone other than the substrate seller.
3. The outcome of the Taiwan reliability evaluation, which SKC has indicated could come by the end of 2026.
4. Independent cost data, which we did not find.

If you are planning a large multi-die part now, treat glass as a parallel study and not a dependency. Our chiplet and advanced packaging lifecycle on The Semiconductor Hub shows where substrate choices and package qualification fall in a programme.

Sources

• Y. Sato (AGC), "Glass Core Substrate", IEEE Electronics Packaging Society, Advanced Substrates Technical Committee note, updated November 2025.
• Y. Lai, K. Pan, S. Park, "Thermo-mechanical reliability of glass substrate and Through Glass Vias (TGV): A comprehensive review", Microelectronics Reliability 161, 2024. Source for the Corning and TSMC (Lin et al., ECTC 2011) work cited.
• X.-B. Le, K.-Y. Yoo, S.-H. Choa, "Numerical Investigation of Crack Suppression Strategies in Ultra-Thin Glass Substrates for Advanced Packaging", Micromachines 16(11), 1256, 1 November 2025.
• C. A. Swenson, "Recommended Values for the Thermal Expansivity of Silicon from 0 to 1000 K", Journal of Physical and Chemical Reference Data 12, 1983.
• Chen et al. (imec, Politecnico di Torino), "Thermal Implications of Non-Uniform Power in BSPDN-Enabled 2.5D/3D Chiplet-based Systems-in-Package using Nanosheet Technology", arXiv:2508.02284, August 2025.
• Corning, "EAGLE XG AMLCD Glass Substrates, Material Information", MIE 301, January 2006.
• Intel, "Intel Unveils Industry-Leading Glass Substrates to Meet Demand for More Powerful Compute", 18 September 2023.
• Shinko Electric Industries, release on its Outstanding Session Paper, "Development of Glass Core Build-up Substrate with TGV", 6 July 2026.
• NIST, "U.S. Department of Commerce Announces $1.4 Billion in Final Awards", 16 January 2025; NIST CHIPS pages on Absolics and on CHIPS funding in Georgia.
• TechSearch International, "Glass Core vs. RDL Interposer Substrates: Ready for Prime-Time?", 3D InCites, 17 July 2025.
• E. J. Vardaman, "Storms Outside, Breakthroughs Inside: High-Performance Packaging Dominates ECTC", Printed Circuit Design & Fab, 30 June 2025.
• TrendForce, "Intel Reportedly Presents First Thick-Core Glass Substrate with EMIB", 26 January 2026.
• SEMI and Global Net report announcement, as carried by EMSNow, 29 May 2026.
• SBS Biz via Daum, 29 May 2026; BusinessWatch via Daum, 4 July 2026; Money Today, 27 July 2026; Seoul Economic Daily, 21 August 2026; Herald Business via Daum, 30 August 2026; CEO Score Daily, September 2026. All read in the original Korean.

The worked examples use illustrative numbers and a deliberately simple model. Vendor figures are the companies' own claims and targets, as published on the dates shown. The timeline view is our judgement as of 7 November 2026.