Where to Catch a Bad Optical Engine in Co-Packaged Optics

When a pluggable transceiver fails, a technician pulls it from the faceplate and fits another. When an optical engine fails inside a co-packaged switch or accelerator, it can take the whole package with it, including a very expensive piece of silicon that was working perfectly. That one difference explains most of what is unusual about testing co-packaged optics (CPO).

The industry's answer is the known good optical engine: prove the engine before it meets the ASIC. The difficulty is that the proof needs light, at speed and over temperature, and a wafer prober was built for none of those. This post goes through where the test is hard, then uses a small cost model to show which test decisions matter most and which are smaller than they look.

The test steps, and what each one can see

There is no standard flow yet. An Advantest presentation at the ECOC 2025 exhibition and a Nexustest paper at SWTest 2026 describe similar sequences, though both sell equipment for this work and split the steps a little differently. The table below is our merged summary. For the basics, see our posts on why co-packaged optics matters for AI and on how wafer probe testing works.

Insertion	Part under test	Typical content	Main limit
PIC wafer sort	Photonic die on the wafer	Electrical and optical DC: power, loss, dark current	Needs optical coupling at the wafer, and says nothing about the finished engine
Engine wafer sort	Photonic and electronic die joined, still on the wafer	DC and interconnect checks in the Nexustest flow	Nexustest lists 1 to 2 sites, and about 80 W per die causing self-heating and warpage
Engine die-level test	Singulated engine with its fibre receptacle	At-speed function, from room temperature to 85 °C	Most of the engine's value is already spent, but it can still be discarded on its own
Module test	Engines packaged with the ASIC	Full functional validation, optical loopback	Nexustest calls these systems non-reworkable, so a failure here is expensive

Advantest's slide states the aim plainly: get a known good optical engine before integration with the SoC. Its list of current problems is just as plain. It says there is no real standard for optical probing, fibre connector handling is all manual, and optical instruments are rack-and-stack setups with heavily customised calibration.

Light needs alignment that probers were not built for

An electrical needle only has to land on a pad. An optical probe has to sit in the right place in all three axes, and at the right angle. A 2024 SWTest paper from IHP and FormFactor puts numbers on the gap: prober XY accuracy of 2 µm and chuck planarity of ±5 µm, against a need for sub-micron placement. So the probe has to search for peak optical power at each site, and that search costs time.

The choice of coupler sets much of what follows. Here are the results that paper reports for one 200 mm test wafer:

Measured on the IHP test wafer	Grating coupler	Edge coupler
Mean coupling loss	3.9 dB ± 0.2 dB	2.8 dB ± 0.1 dB
1 dB optical bandwidth	38 nm ± 7 nm	More than 200 nm
Fabrication and handling	No extra steps	Needs a trench, here over 95 µm wide and 60 µm deep

The edge coupler's numbers are better, but it brings new ways to fail. The authors check trench quality first so the probe lens is not damaged, and they excluded some dies because of trench imperfections. FormFactor co-wrote this paper and sells the system, so treat it as a strong demonstration on one wafer.

There is also a coverage question. Our reading is that a grating coupler added only for test can pass while the edge coupler the product will actually use goes unexercised. Ask of every optical test structure whether it shares a light path with the product.

A peer-reviewed paper published in Chips in August 2026, by authors from Politecnico di Milano and the probe card maker Technoprobe, shows why alignment is more than a mechanical issue. It compares search routines across 72 simulated scenarios built from measured coupling data. Exhaustive scans never missed the peak but were judged unusable for volume production. The recommended gradient routine converged in 95.8% of scenarios and reached 99.4% of peak power. Read the other way, about one case in 24 did not converge, so a production flow needs a retry rule for failed alignments.

The same paper notes that a brief vibration during an optical measurement can be logged as an insertion loss failure on a device that is fine. The authors say that the benefit of their proposed sensors still has to be measured.

Fibre attach changes what you are testing

An engine tested through a probe is not the same optical path as an engine with fibres on it. Fibre attach adds its own loss, and it is slow. A 2023 Optics Express paper from the University of Rochester describes multi-port optical packaging as slow and expensive, puts the state of the art for a two-fibre array at more than 1.3 dB, and reports its own laser fusion splicing method at a minimum of 1.1, 1.5 and 1.4 dB per facet for 2, 4 and 8 fibres. That is research, and the joint is permanent.

Permanent joints are awkward for test because every later step must handle the fibres. This has pushed work toward separable connectors. A US Conec conference paper describes an expanded beam interface, 50 µm across, that lets the PIC and the fibre connector be tested independently. It models 98% of insertion loss values below 2.8 dB, with average lens shifts of 0.3 µm and 1.1 µm after three solder reflow cycles.

A connector also relaxes the test socket. Nexustest specifies ±10 µm system alignment for its die-level handler, which takes engines fitted with a receptacle, and claims about 570 units per hour on four sites. Compare that with the sub-micron search above. The price appears later: a 2026 arXiv preprint by Yi and Wilkerson warns that connectorised approaches add interfaces whose reliability must be proven at scale.

NVIDIA has taken this route in public. Its January 2026 developer blog describes screening optical components before they are attached to the switch silicon, with fibres fitted at the final stage through a detachable connector. It goes on to claim a "guaranteed 100% yield". The blog gives no data behind that phrase, so we read it as a statement of intent about screening, not a measured result.

Lasers and burn-in

Lasers are the part most likely to be designed out of the package altogether. The OIF ELSFP agreement (version 2.0, January 2025) gives the reason: lasers have historically had much lower maximum reliable junction temperatures than silicon. A faceplate module separates the laser from the heat of the ASIC and can be replaced in the field through a blind-mate connector. It also has to keep the system at IEC 60825-2 Hazard Level 1. Its named optical power classes run from 11 dBm to 26 dBm per wavelength per fibre core, which is about 13 mW to 398 mW, so eye safety is a practical matter on any test floor handling these parts.

Burn-in is the classic screen. Our primer on burn-in testing covers the general method. For lasers, two Finisar patents give useful background, though they are old and do not concern CPO. One says 2% to 10% of some laser populations fail early from manufacturing defects, and describes conventional burn-in at about 85 °C or higher and about twice normal bias current. The other says suitable conditions are found by trial and error, which can take a year or more.

Moving the laser changes where this work falls. With an external source, laser screening can stay in the laser module's own flow. With an integrated laser, it has to happen at wafer or engine level. A 2021 review in Electronics by Buffolo and colleagues finds that III-V lasers bonded to silicon share the epitaxy-related degradation of conventional laser diodes, while quantum dot lasers grown on silicon are limited mainly by misfit dislocations. Our reading is that one screen should not be assumed to suit both.

The silicon side is being burned in as well. Aehr said in March 2026 that a repeat customer had ordered wafer-level systems for silicon photonics, testing up to nine 300 mm wafers at up to 3,500 W per wafer, and it claims earlier detection of infant mortality at lower cost than package-part testing. The release gives no figures for that saving.

A worked example: what one bad engine costs

Every number in this section is an illustrative assumption, not data from any vendor or product. Assume a package with eight optical engines and a $20,000 ASIC, with $1,000 of substrate and assembly. Assume no rework once the engines are attached. An engine has accumulated this much cost at each step:

Where the bad engine is caught	What is lost	Cost
PIC wafer sort	The photonic die	$40
Engine wafer sort	Photonic and electronic die, bonding	$120
Engine die-level test	The complete engine with receptacle	$200
Module test	$200 engine + $1,400 for seven good engines + $20,000 ASIC + $1,000 assembly	$22,600
In the field	Module cost + $2,000 for removal and replacement, before any lost service	$24,600

The step that dominates is the one onto the ASIC: $22,600 is 113 times $200. Everything before it is small by comparison. Now see how that plays out across a build, with 5% of engines defective on arrival at die-level test. Yield is (1 minus the escape rate) to the power of 8, because all eight engines must be good.

Flow	Test cost per engine	Escape rate	Cost per engine used	Package yield	Cost per good package
No engine test	$0	5%	$200.00	66.3%	$34,066
90% coverage	$15	0.52%	$225.13	95.9%	$23,779
99% coverage	$25	0.053%	$236.72	99.6%	$22,990
99% coverage, 3% false rejects	$25	0.054%	$244.03	99.6%	$23,052

To see one row in full, take 99% coverage. Of every 100 engines tested, 95 are good and pass, and 0.05 are bad and pass, so 95.05 go forward. The escape rate is 0.05 divided by 95.05, or 0.053%. Each engine used costs $225 divided by 0.9505, or $236.72. A package costs $21,000 plus eight of those, or $22,894, and dividing by a yield of 99.58% gives $22,990.

Three lessons follow, within this model:

• Some engine test is worth far more than the rest. Going from no test to 90% coverage saves about $10,287 per good package.
• Coverage still pays. Spending $10 more per engine to go from 90% to 99% saves another $789 per good package.
• False rejects are a smaller cost here. Throwing away 3% of good engines adds about $62. It would matter more if engines cost far more than $200.

What about moving the catch from die-level test back to PIC wafer sort? If all 5% of defects came from the PIC and wafer sort found them all, the saving would be 5% of ($200 minus $40), or $8 per engine, which is $64 across eight engines. So an optical wafer sort step would have to cost less than about $8 per die to pay for itself on scrap alone. That is a much weaker case than testing before the ASIC, and defects introduced after the PIC would not be caught at all. Wafer sort may still earn its place through process learning.

Burn-in has its own sum. Suppose 0.5% of engines carry a latent defect that passes every test and fails in the field. Then 1 minus 0.995 to the power of 8, or 3.93%, of packages fail, costing 3.93% of $24,600, or about $967 per package shipped. A $20 burn-in on eight engines costs $160. It pays in this model if it removes those defects and does no harm, and both of those conditions need proving.

Serviceability beside an expensive chip

Yi and Wilkerson put the operational change directly: pluggable optics are among the most often replaced parts in a data centre, while a degraded co-packaged interface may mean replacing a whole package or board. An ELSFP laser module is designed for field replacement. A detachable fibre can be handled on its own. The engine itself, in the non-reworkable designs described above, cannot be swapped.

That raises the bar for field reliability data, and the public data is still thin. Broadcom said in October 2025 that Meta had run CPO for one million cumulative 400G-equivalent port device hours with no link flaps, in a high-temperature lab environment, citing an ECOC 2025 paper. NVIDIA's Hot Chips 2025 slides claim 13 times better laser reliability and four times fewer lasers. Both are vendor claims, and neither document gives the test method.

A result of zero events also has limits. Using the standard rule of three, zero events in one million port-hours gives a 95% upper bound of about three events per million port-hours, assuming independent events at a constant rate. Applied to 100,000 ports over a year (876 million port-hours), that bound allows up to about 2,628 flaps. This is our arithmetic and not a forecast. It only shows what a clean result of that size cannot rule out. Flaps are also not the same as hard failures.

Questions to settle before design freeze

1. What does a module scrap cost you? Replace our $22,600. Every other test budget follows from it.
2. Which test sees each defect type? List the defects by origin (PIC, bonding, receptacle, attach), then mark the first insertion that can detect each one.
3. Do the test structures share a light path with the product? Couplers, trenches, fiducials and loopback paths have to go on the mask early. Our chiplet and advanced packaging lifecycle on The Semiconductor Hub shows where known-good-die test falls in a programme.
4. What fails only at speed or when hot? If those defects matter, wafer sort alone will not produce a known good engine.
5. How will you separate the tester from the device? Agree retest rules for failed alignments, and correlate loss readings between insertions.
6. What can be replaced in the field? Decide on lasers and fibre with the service team in the room.

Sources

• D. Malsam (Advantest), "HVM Testing for Silicon Photonics and Co-Packaged Optics Devices: Challenges and Solutions", ECOC exhibition presentation, 2025 (vendor).
• A. H. Tan, J. Lin and T. Jin (Nexustest), "Enabling Die Level KGD Testing for CPO Optical Engine", SWTest, June 2026 (vendor).
• A. Peczek et al. (IHP) and D. Rishavy et al. (FormFactor), "Optical edge coupling method for fully automated PIC wafer-level testing", SWTest, June 2024.
• M. Bejani, D. Appello, M. Mauri and S. Mariani, "A Smart, Sensor-Augmented Probe Card for Wafer-Level Photonic Testing of Co-Packaged Optics Devices", Chips 5(3), 21, 2 August 2026.
• J. Nauriyal et al., "Fiber array to chip attach using laser fusion splicing for low loss", Optics Express 31(13), June 2023.
• M. Hughes et al. (US Conec), "A Single-Mode Expanded Beam Separable Fiber Optic Interconnect for Silicon Photonics", conference paper (vendor).
• OIF, "OIF-ELSFP-02.0: External Laser Small Form Factor Pluggable Implementation Agreement", 8 January 2025.
• Finisar, US patents 6,977,517 (granted December 2005) and 8,067,949 (granted November 2011), background sections.
• M. Buffolo et al., "A Review of the Reliability of Integrated IR Laser Diodes for Silicon Photonics", Electronics 10, 2734, 2021.
• Aehr Test Systems, press release on follow-on wafer-level burn-in order, 3 March 2026 (vendor).
• Y. Yi and D. Wilkerson, "3D optoelectronics and co-packaged optics: when solving the wrong problems stalls deployment", arXiv:2603.21313, March 2026 (preprint).
• NVIDIA, "Scaling Power-Efficient AI Factories with NVIDIA Spectrum-X Ethernet Photonics", developer blog, 6 January 2026, and G. Shainer, Hot Chips 2025 slides (vendor).
• Broadcom, "Broadcom Showcases Industry-Leading Quality and Reliability of Co-Packaged Optics", press release, 1 October 2025 (vendor).

The worked example uses illustrative numbers, and the rule of three calculation is ours. Vendor figures are the companies' own claims, as published on the dates shown.