Beyond Copper: Ruthenium, Molybdenum and the BEOL Resistance Wall

Bulk ruthenium conducts about four times worse than bulk copper, and bulk molybdenum about three times worse. Both are still serious candidates for the tightest metal layers of future logic. The reason is that a 10 nm wire does not behave like a block of metal, and a copper wire of that width is only about half copper.

This post works through the resistivity against line width with a simple published model, shows which inputs decide the answer, and then sets out what each alternative costs in reliability and integration.

Copper pays twice

The first penalty is the size effect. Electrons in copper travel about 40 nm between phonon collisions at room temperature. Once a wire is narrower than that, they hit walls and grain boundaries far more often than they hit phonons. The Fuchs and Sondheimer model covers surfaces, with a specularity parameter p, where p = 0 means fully diffuse. The Mayadas and Shatzkes model covers grain boundaries, with a reflection coefficient R.

The second penalty is geometry. Copper needs a diffusion barrier and a liner, because it detaches and drifts into low-k dielectrics. An imec tutorial from June 2024 puts the floor for that combined stack at about 2 to 3 nm, below which it stops doing its job. The stack conducts poorly and does not shrink with the wire. Copper dual damascene is also limited to aspect ratios of 2 to 3 by the fill process, and etching copper remains highly challenging, so a taller line is no easy way out.

Here is the volume effect alone, for a trench twice as tall as it is wide, with a 2 nm stack on the floor and both walls for copper and a 0.3 nm adhesion layer for ruthenium:

Trench width	Trench area	Copper share of the trench	Ruthenium share of the trench
30 nm	1,800 nm²	84%	98%
20 nm	800 nm²	76%	96%
10 nm	200 nm²	54%	93%

The figure of merit that reorders the table

In these models, a wire much narrower than the mean free path has a resistivity set by the product ρ₀λ, not by ρ₀ alone. A short mean free path means walls and boundaries cost less, because electrons were scattering often anyway. That is how a poor bulk conductor can make a good narrow wire.

Metal	ρ₀ (µΩ·cm)	λ (nm)	ρ₀λ (10⁻¹⁶ Ω·m)	Melting point (K)	Cohesive energy (eV)
Copper	1.68	40.7	6.8	1358	3.8
Molybdenum	5.3	10.9	5.8	2895	9.5
Ruthenium (range by crystal direction)	5.7 to 7.4	6.7 to 6.9	3.8 to 5.1	2606	8.0

The values are from Table 2 of the imec tutorial. The gap in ρ₀λ is modest. The tutorial is direct about this: ruthenium's line resistance benefit comes mainly from the extra conductor volume, with resistivity scaling as the necessary second contribution.

There is also a catch in R. Fitted values differ by metal: about 0.20 to 0.25 for copper, 0.43 to 0.58 for ruthenium and 0.46 for molybdenum, according to a 2022 imec study of ultrathin molybdenum. Refractory metals lose more at each boundary and are hard to grow with large grains at low thermal budgets. Dutta and colleagues likewise found grain boundaries dominant in ruthenium wires of 30 to 130 nm².

Worked example: line resistance from 30 nm to 8 nm

The geometry and inputs follow the 2018 paper by Milosevic, Kerdsongpanya and Gall. The trench has width w and height 2w. A liner of thickness t sits on the floor and both walls, so the conductor is W = w − 2t wide and H = 2w − t tall. Surfaces are fully diffuse (p = 0) and R = 0.4 for every metal.

Input	Copper	Ruthenium	Molybdenum	Source
ρ₀ (µΩ·cm)	1.7	7.6 (basal plane)	5.3	Milosevic; imec tutorial for Mo
λ (nm)	39	6.7	10.9	Milosevic; imec tutorial for Mo
t (nm)	2.0	0.3	0	Milosevic; barrierless Mo per imec

The paper uses approximate forms of the two models without printing them. We tested candidate forms against its published numbers, and this one, with grain spacing set equal to conductor width, fits well enough to redo by hand:

ρ = ρ₀ + ρ₀λ × [0.75 × (1/W + 1/H) + 1/W]

The 1/W term is the first-order Mayadas and Shatzkes correction, 1.5 × R/(1 − R) × λ/W, which equals λ/W at R = 0.4. The ρ₀λ product now appears on its own, which is the figure of merit at work. Treat this as our fit to a published calculation and not as an equation from the paper. Line resistance then follows from R′ = ρ/(W × H). With ρ in µΩ·cm and dimensions in nm, R′ in Ω/µm is 10,000 × ρ/(W × H).

Copper at w = 10 nm, by hand: W = 6, H = 18. The surface term is 0.75 × 39 × (1/6 + 1/18) = 6.5. The grain term is 39/6 = 6.5. So ρ = 1.7 × (1 + 6.5 + 6.5) = 23.8 µΩ·cm, and R′ = 10,000 × 23.8/108 = 2,204 Ω/µm.

Ruthenium at the same width: W = 9.4, H = 19.7. The surface term is 0.75 × 6.7 × (1/9.4 + 1/19.7) = 0.79. The grain term is 6.7/9.4 = 0.71. So ρ = 7.6 × 2.50 = 19.0 µΩ·cm, and R′ = 10,000 × 19.0/185 = 1,027 Ω/µm.

Width w	Cu ρ	Cu R′	Ru ρ	Ru R′	Mo ρ	Mo R′
30 nm	7.0	46.6	11.3	64.2	9.4	52.2
20 nm	10.3	169	13.2	171	11.4	143
15 nm	14.0	455	15.1	352	13.5	300
12 nm	18.5	1,050	17.0	630	15.5	539
10 nm	23.8	2,200	19.0	1,030	17.6	879
8 nm	34.3	6,120	22.1	1,900	20.6	1,610

ρ is in µΩ·cm and R′ in Ω/µm, rounded to three figures.

The paper publishes 2,090 Ω/µm for copper at 10 nm and 1,020 Ω/µm for ruthenium, so our form runs about 5% high on copper and under 1% high on ruthenium. It places the ruthenium and copper crossover at 19.7 nm against the paper's 19 nm, and a 2020 first-principles study with thicker copper liners finds alternative conductors ahead below about 21 nm. At 8 nm our ruthenium advantage is about 3.2 times, while the imec tutorial's calibrated model gives about 3 times at aspect ratio 3, a different geometry.

Which input moves the answer most

The copper stack does. Holding everything else fixed:

Copper barrier and liner	Copper share at w = 10 nm	Cu R′ at w = 10 nm	Ru and Cu crossover
1.0 nm (below the stated floor)	76%	1,240 Ω/µm	13.3 nm
1.5 nm (below the stated floor)	65%	1,620 Ω/µm	16.7 nm
2.0 nm	54%	2,200 Ω/µm	19.7 nm
3.0 nm	34%	4,950 Ω/µm	25.0 nm

R is next. Using metal-specific values of 0.25 for copper, 0.5 for ruthenium and 0.46 for molybdenum instead of a common 0.4, the crossover with copper falls to 13.6 nm for ruthenium and 16.9 nm for molybdenum. At w = 10 nm the three lines become 1,690, 1,170 and 959 Ω/µm. Any quoted crossover depends heavily on assumed barrier thickness and grain quality.

The molybdenum column deserves the most suspicion, because the model flatters it. It assumes no liner, no oxide and grains as wide as the line. Published work points the other way on two of those. An imec paper at IITC 2022 lists 10 nm ALD molybdenum at 19 to 22 µΩ·cm, already above our 17.6 for a more confined 10 nm line. The 2022 thin-film study found a native oxide of about 2 nm after air exposure, with about 0.95 nm of metal lost in a month. As an illustration, if a 10 nm line lost 1 nm from its top and each wall, W = 8 and H = 19, ρ rises to 20.2 µΩ·cm and R′ to 1,330 Ω/µm, a rise of about 50% that puts it behind ruthenium.

Measured silicon can also beat the model. At IEDM 2023, imec reported ruthenium lines at 10 nm critical dimension and aspect ratio 6 at 235 Ω/µm, 75% below its simulated copper line at aspect ratio 2. At nominal dimensions of 10 nm by 60 nm, that implies about 14.1 µΩ·cm. Our formula gives 17.1 µΩ·cm and 286 Ω/µm, so it is about 20% pessimistic here, and height does much of the work.

What each metal costs

	Copper	Ruthenium	Molybdenum
Barrier need	Barrier plus liner, floor about 2 to 3 nm	No barrier, 0.3 nm TiN adhesion layer works	No barrier or adhesion layer on SiO₂, organosilicate glass or SiCO
Line formation	Damascene with mature CMP, etch very hard	Direct etch with good sidewall control, new flow	Barrierless fill shown down to 10 nm critical dimension
Electromigration evidence	Voids nucleate at the top dielectric interface	No failures forced above 30 MA/cm² at 21 nm pitch	No failures after more than 600 h at 330 °C and 5 MA/cm², in Mo-Ru hybrid structures
Main weakness	Cross-section lost to the stack	Yield at tightest pitch, new flow, material footprint	Surface oxidation, impurities, grain size

Ruthenium: strong reliability, expensive change

Electromigration activation energy follows the bonding strength of the lattice, and ruthenium's cohesive energy is about twice copper's. In work the tutorial cites, voids appeared only at 150 to 200 MA/cm², with self-heating of about 260 °C. With a 0.3 nm TiN layer there was no metal drift, and dielectric breakdown (TDDB) results support a 10-year lifetime at k = 3.0. An imec paper at IITC 2022 reports semi-damascene ruthenium with air gaps passing a 10-year TDDB lifetime above 0.75 V at 100 °C. Kim and colleagues (2023) also conclude that ruthenium is more reliable than copper.

The price is in manufacturing. Ruthenium's advantage grows with direct metal etch and tall lines, a different module from damascene, and yield falls with pitch. At IITC 2022 more than 90% of devices met a target below 700 Ω/µm at 20 to 26 nm pitch, and about 50% at 18 nm. In its June 2025 release, imec reports an average of 656 Ω/µm at 16 nm pitch, with 40% of those structures meeting the target and yields of 90% or higher at 18 to 22 nm. Tall, closely spaced lines also raise capacitance, which is where air gaps enter. An imec article from September 2023 reports simulations of 30% more metal line self-heating with air gaps.

imec aims this flow at the first local metal layer of A7 and later nodes, and wide lines stay copper, as the table shows at 30 nm. Its IITC 2026 programme lists papers on the transition from a ruthenium direct-etch layer to a copper single-damascene layer and on process-induced TDDB effects at 18 nm pitch. Only the titles were available to us.

The material carries a cost too. The tutorial's sustainability table gives 26 kg CO₂ per cm³ of ruthenium produced, about a thousand times copper's 0.0251, against 0.0583 for molybdenum. Its supply concentration index reads 8,718 for ruthenium, 1,097 for copper and 2,266 for molybdenum.

Molybdenum: cheap and strong, but chemically touchier

Molybdenum has the highest cohesive energy of the three. It adheres well, above 5 J/m² on low-k dielectrics in the 2022 study, with no drift into SiO₂ or SiCO. Its thin-film resistivity beats a TaN/Cu/TaN stack only below about 8 nm of total metal thickness, and the study's conclusion is conditional: promising if surface oxidation and impurities can be kept under control. The tutorial makes the wider point that surface oxidation must be avoided in lines under 10 nm, and it counts ruthenium's resistance to oxidation as an advantage. That means extra steps, such as the preclean without an air break that imec used to remove MoOx.

Lam Research's February 2025 release for its ALTUS Halo tool quotes Micron on bringing molybdenum into mass production, and claims better than 50% improvement in resistance in most instances. That comparison is with tungsten, and the volume applications named first are 3D NAND. imec's ALD work likewise targets tungsten and cobalt in middle-of-line contacts and rails. Molybdenum's established path is replacing tungsten. We found no primary source showing either molybdenum or ruthenium lines replacing copper in volume logic production as of November 2026.

What a design team should take from this

Metal choice sits with the foundry, but the consequences reach block design.

1. Ask for line and via resistance per layer, with the liner assumption. The table above moves by a factor of four on 2 nm of stack thickness, so a bare claim about a new metal tells you little.
2. Do not assume resistance is monotonic up the stack. A hybrid stack may change metal at a layer boundary, with its own via resistance. imec reports a median of about 33 Ω for vias landing on its aspect ratio 6 lines. Early estimates built on older habits such as wire load models are a poor guide here, so plan on extracted parasitics.
3. Treat tall lines as an RC question. Lower R with higher C can help long wires and hurt short, capacitance-dominated ones. Run both on your own net length distribution.
4. Read this alongside the power network. The thin lower layers are where voltage drop concentrates, so backside power delivery relieves the same layers that new metals target. Budget the two together, along with the choice of gate-all-around node they arrive with.

Our SoC lifecycle on The Semiconductor Hub shows where these node and stack decisions fall in a programme.

Sources

• Soulié et al. (imec), "Selecting Alternative Metals for Advanced Interconnects", arXiv:2406.09106, 13 June 2024.
• Milosevic, Kerdsongpanya and Gall (Rensselaer Polytechnic Institute), "The Resistivity Size Effect in Epitaxial Ru(0001) and Co(0001) Layers", 2018 IEEE Nanotechnology Symposium.
• Founta et al. (imec, KU Leuven, Ghent University), "Properties of ultrathin molybdenum films for interconnect applications", Materialia, 2022.
• Dutta, Moors, Vandemaele and Adelmann, "Finite Size Effects in Highly Scaled Ruthenium Interconnects", arXiv:1712.03859, December 2017.
• Philip et al., "First principles evaluation of fcc ruthenium for use in advanced interconnects", arXiv:2001.02216, version of March 2020.
• Gupta et al. (imec), "Two-metal-level semi-damascene interconnect at metal pitch 18 nm and aspect-ratio 6 routed using fully self-aligned via", IEDM 2023, abstract.
• Kim et al., "Electromigration Reliability of Barrierless Ruthenium and Molybdenum for Sub-10 nm Interconnection", ACS Applied Electronic Materials, 2023, abstract.
• imec, IITC 2022 paper abstracts (Gupta, Hosseini, Pokhrel, Lesniewska and colleagues), imec event page, June 2022.
• imec, press release on 16 nm pitch ruthenium lines, 3 June 2025 (company technical release).
• imec, "Mitigating the thermal bottleneck in advanced interconnects", 28 September 2023 (company technical article).
• imec, IITC 2026 programme listing, June 2026, titles only.
• Lam Research, "Lam Research Ushers in New Era of Semiconductor Metallization with ALTUS Halo for Molybdenum Atomic Layer Deposition", press release, 19 February 2025 (company claims).

The line resistance formula is our own fit to published calculations, using sourced inputs, and it ignores vias, line edge roughness and conduction in the liner. The oxide case is illustrative. Vendor and imec figures are the organisations' own results and claims, as published on the dates shown.