Processors
Praveen Vishakantaiah, president of Intel India, said one innovation in the area of frugal engineering could soon be in the market. "With HCL, we have launched a nettop with a battery backup in the power adaptor. It's a three hour backup that helps in areas that do not have continuous power supply. The innovation was in the adaptor; if we had done it in the nettop, it would have raised the cost significantly," he said. The past d…
by
Murugavel Ganesan
December 14, 2010
News
Intel dominates the business of PC processors. But as consumers shift increasingly to tablets and smartphones, the company is trying to quickly move to serve those devices. On a visit to Bangalore last week, Justin Rattner, CTO of Intel, talked exclusively to TOI on a range of issues, from the nature of work its Bangalore labs are being asked to do, to some really futuristic, almost sci-fi, stuff. More at this link from Times of India!
by
Murugavel Ganesan
December 14, 2010
SoC Design
There are plenty of really good, proven processor cores on the market today. But if you have more than simple control tasks, perhaps you've considered using a processor that you can customize. This paper discusses 10 good reasons why you should consider customizing your core in your next SoC design.
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Murugavel Ganesan
December 02, 2010
Semiconductor Industry
The average base salary among the North American engineers surveyed totaled just over $100,000; annual compensation, including bonuses and overtime pay, averaged $107,300, according to our findings. North American engineers also reported the highest job satisfaction (64 percent) among the respondents. In China and India (where base salaries for engineers in most cases remain far lower than in the other surveyed regions), bonus figures for Chines…
by
Murugavel Ganesan
November 30, 2010
Semiconductor Business
Femtocells are small, low power cellular base stations that extend coverage indoors where signals are weak. Broadcom Corp. has signed a definitive agreement to acquire Percello Ltd., a privately-held company that develops system-on-a-chip (SoC) solutions for femtocells, for $86 million in cash.
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Murugavel Ganesan
October 28, 2010
Semiconductor Industry
We are in the fourth quarter and the outlook is cloudy for the rest of 2010 and heading into 2011. Here are some good and bad signs for the electronics industry.
by
Murugavel Ganesan
October 28, 2010
Semiconductor Manufacturing
A New York state agency plans to take over a technology park that houses the new 300-mm fab owned by U.S. silicon foundry upstart GlobalFoundries Inc. GlobalFoundries' wafer fab under construction in New York state, Fab 8, would run the 22-nm production and more advanced nodes. Construction for Fab 8 started in July of 2009. The fab will have 60,000 wafer starts per month once it goes into full production. Production is expected to go onl…
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Murugavel Ganesan
October 27, 2010
Semiconductor Manufacturing
Is Intel preparing to push the issue with regard to its desire to move to 450-mm wafer sizes? One analyst thinks so . While most equipment is nowhere near ready at this stage (development has been limited ), C.J. Muse, an analyst with Barclays Capital, thinks the No. 1 chipmaker could specify that its newly announced D1X development fab in Oregon will be 450-mm capable (meaning it can accommodate 450-mm processing when/if the equipment becomes a…
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Murugavel Ganesan
October 27, 2010
Processors
Last week i was invited to a Tech Talk organized by Oracle India (Sun Microsystems BU). The title of the talk was "Tech Talk - The Bleeding Edge, Evade your challenges– A dive into critical issues affecting High-end bleeding edge Semiconductors designs and the development engineers face off". The speaker was Mr. Sridhar Vajapey, VP, Hardware Development (Sun Microsystems BU), Oracle Corporation Inc. The talk was highly informative co…
Semiconductor Business
Infineon's Wireless Solutions unit has been working together with the Dresden design house "Blue Wonder" on the development of LTE technologies for one and a half years. Now Infineon has taken over the Saxony-based company together with its 50 employees. Blue Wonder describes itself as a design house for LTE-IP and mobile communications solutions serving the telecommunications and semiconductor industries. Blue Wonder’s team is …
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Murugavel Ganesan
October 20, 2010
SoC Design
Today we are in the age of Digital Convergence seeing a major change in the way digital electronics systems are designed. Examples of such convergence can be seen in Microsoft's Xbox (From IT/Games to Home Entertainment), Apple's iPhone (From IT to Telecommunication/Entertainment), and Sony's Vaio (From Consumer Electronics to IT). This innovative look at technology has redefined road maps and business objectives of major corporation…
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Murugavel Ganesan
September 16, 2010
Embedded Systems
Hardware design specialist Libelium opens a new community site for electronics enthusiasts offering a wide range of tutorials, cost-effective products, news, customer service and user-created hacks & recipes. Libelium, a leading wireless and electronics innovator, announces the launch of the Cooking Hacks website. Drawing on the similarity between cooks exchanging recipes and engineers sharing hacks, the new website offers a wide range of …
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Murugavel Ganesan
September 16, 2010
Video
In march we had an article covering the Italian project made to fill the gap between Embedded Low Cost and Wireless. Today we have the first video review! Check it out.
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Murugavel Ganesan
September 16, 2010
Verification
A peer code review of RTL, testbench and test cases is a structured read of the code by colleagues, checked against the specification and the verification plan, before the code is relied on for sign-off. It finds bugs that simulation has not yet exercised, enforces coding guidelines and spreads knowledge across the team. On its own it cannot prove 100% verification closure, but it covers the gaps that simulation, coverage and formal tools leave,…
Video
The Indian Institute of Science (IISc) and IITs, the premier engineering colleges of India, have earlier joined hands to produce the world's largest repository of technical video lectures and web-based courses geared towards science and engineering students. The IIT and IISc faculty have recorded around 4,750 videos for this project till date and anyone, anywhere can watch the lectures online through YouTube at http://youtube.com/iit . [via]…
Power Electronics
Say YES for changing ONE light to LED at home. Get your organization to say YES to change ONE light per employee to LED and to encourage each employee to adopt ONE light for home. To know more and to say YES, see the brochure at http://bit.ly/aJyQHp If you can reach your organization to implement LED lights and to encourage employees to adopt LED lights through this campaign, leave a comment indicating name of the organization /department and…
by
Murugavel Ganesan
September 01, 2010
Semiconductor Business
As per the management email sent to Infineon employees this morning, Infineon and Intel have signed the contracts related to the sale of Infineon's Wireless business to Intel Corporation for a sum of approximately US Dollars 1.4bn. Initial reports suggest that IFX's Wireless division is to become a standalone business including all related functions within the Intel group. According to the latest status they expect around 3,400 Infineon …
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Murugavel Ganesan
August 30, 2010
Opinion
Linley Gwennap says "Making it clear that money is no object in its quest to become a major player in the smartphone market, Intel plans to acquire the wireless operations of Infineon. The deal is firm but has not yet been announced, as final details are being negotiated. We believe the purchase price exceeds $1.2 billion, ranking it as one of Intel’s largest acquisitions ever. Infineon’s cellular and GPS technology will complement Intel’s…
by
Murugavel Ganesan
August 04, 2010
Semiconductor Industry
Our company today hosted a renowned motivational speaker Mr. John Foley of Blue Angels fame. The title of the talk being "Learn High Performance from a Fighter Pilot", he talked about High Performance and how The Blue Angels way of management, precision, trust and team work can help companies build high performance teams. His energy was profound and kept the audience captivated by the visuals from the FA-18 Hornet's cockpit, the …
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Murugavel Ganesan
July 07, 2010
Jobs
Infineon Technologies India Pvt Ltd has some openings for full time and contract positions. If you are interested in applying for these positions, please email us directly with the title of the job description as the subject for faster processing. Please don't email us to inquire about the status. If you are shortlisted, you will be contacted by the company or the hiring manager directly. Please click on the title for more info. Full Time…
by
Murugavel Ganesan
July 07, 2010
News
ip.access, the leading developer of femtocell and picocell solutions, and AlertMe.com, the pioneer in home energy management systems, have created a demonstration showing how femtocells can be integrated into smart home energy management solutions. With femtocell integration, the AlertMe Energy service can automatically detect when phones enter or leave the house and can therefore power down lights, televisions and other home appliances a…
Synthesis
The High Level Synthesis Blue Book is a comprehensive guide for designing hardware using C++. It is targeted to RTL designers that are currently using, moving, or planning to move, to an HLS design environment. Check the blog post by Thomas Bollaert and More here . The High-Level Synthesis Bluebook is available online by clicking here . Author Michael Fingeroff will also be hosting a free webinar on June 23rd where he will be presenti…
News
This new model available in black or white from June 24 has an unchanged pricing at $199 for the 16GB model and $299 for the 32GB model. Features include the A4 processor (heart of the iPad), Multitasking, retina display for high resolution viewing, HD video recording and editing , 3-axis gyro, tracking pitch, roll and yaw: perfect for video games, battery life of 7 hours theoretical talk time and 6 hours of 3G web browsing, dual microphone, an …
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Murugavel Ganesan
June 09, 2010
Semiconductor Industry
Click on the title for the full list!
by
Murugavel Ganesan
June 07, 2010
India Semiconductors
The conference schedule and the registration links can be found here . With a program that is focused on helping you deal effectively with every day design challenges, SNUG is committed to making the best possible use of your time and delivering practical information you can take away and apply to your current project as well as future designs. CLICK HERE to register in advance. If you cannot attend the full program, please register for the ses…
Physical Design
In this blog post, we will discuss some of the challenges and techniques involved in designing a clock network for a very large scale integration (VLSI) circuit. A clock network is a special type of interconnect that distributes the clock signal to all the synchronous elements in the circuit, such as flip-flops, latches, and registers. The clock signal is used to synchronize the operation of these elements and ensure correct functionality and ti…
Physical Design
The objective here is to explore placement techniques which can lead to reduction in IR drop. One way to do this is to place high current cells towards the periphery in a peripheral i/o design. Simple way to implement this is to have a fixed dummy block at the center of the chip and attach fake nets from it to cell instances in a DEF file. A commercial placer can then be used to place this netlist. After placement, fake blocks and nets can be de…
Static Timing Analysis
Clock skew variation is the spread in clock skew between two flip-flops caused by process, voltage and temperature (PVT) variation, on top of the nominal skew the clock tree was designed for. It is estimated in three main ways: statistical models built from the delay spread of each clock buffer and wire, simulation across corners and Monte Carlo samples, and measurement on silicon. The estimate matters because every picosecond of skew variation …
Static Timing Analysis
How can you quantify the impact of dummy fill on post-layout timing? Dummy fill can be inserted into a layout using SOC Encounter or post-tape-out tools like Calibre/Assura. You should then extract dummy fill using Fire-n-Ice extractor and compare pre-fill and post-fill timing. Can you compare the impact of filling approaches (grounded vs. floating)?
Static Timing Analysis
Whitespaces (empty space) are inserted in layouts in order to increase the routing resources of the chip. Have you ever studied the impact of whitespace (and aspect ratio) on timing and wirelength, by say increasing the whitespace from 0% to 100% and evaluate the impact on both wirelength and timing. Can you predict how this will look like? For a 300 mm wafer, can you parameterize the relationship between the number of dies produced, timing, die…
Static Timing Analysis
Timing analysis inaccuracies due to crosstalk, multiple gate input switching, supply voltage variation, temperature, manufacturing variation, etc. are very common. How do you tackle them in real life designs? How do you do it using Prime Time (PT)?
Static Timing Analysis
How do you observe and highlight the impact of assumptions on gate-length variability distributions (if any) on final design timing distributions. How do you implement a simple statistical timer by (say) 500 Monte Carlo runs of STA (e.g. Primetime). Assume independent gate delays. Assume gate-delay distributions and generate circuit delay distributions. Delays can be changed in the SDF file. Interconnect may be ignored. Can we try tem for a few …
Synthesis
How do you quantify the effect of WireLength Models (WLM) and target frequency on the post-routing timing results?
Physical Design
Power gating adds enabling signals to a power supply network; dynamic power supply management adjusts supply voltage according to data path criticality. You are asked to take a testcase and upgrade its power supply network to dynamic power supply. How can you verify the power reduction of your technique?
Physical Design
Constructing a zero-skew clock tree can be formulated as constructing a path-length balanced tree (assuming path delay is proportional to path length), i.e., to have identical path length between the root and any leave of the tree. The problem can be in a Euclidean plane, a rectilinear plane, or with other distance metrics. This problem's computation complexity is open. Can you find an approximation algorithm for the problem which guarantees…
Physical Design
Clock skew is a function of process variation, i.e., delay from the clock source to a leave of the clock tree is a statistical function. A rule of thumb for minimum process variation clock tree design is to have balanced branches, i.e., identical buffers from identical distances to the clock source, and symmetric clock routing branches with identical capacitive loads. Can you have a more flexible clock tree design scheme, while maintaining a min…
Static Timing Analysis
Modern clock networks include several drivers in which delays are affected by the timing of their input signal transitions. How do you find out the input alignment of clock network drivers which leads to worst case driver gate delays?
Synthesis
Re-timing reduces longest combinational logic paths by relocating some of the flip-flops, both logically and physically. How do you evaluate the effectiveness of re-timing, with existing tools and/or some of your own scripts? Comparing with useful clock skew is a plus.
Synthesis
This is a process of combining several cells to form new library cells, and to optimize a transistor level netlist. This can be done algorithmically (e.g. pattern matching) or in an ad-hoc fashion. You can verify your area saving, timing improvement and power consumption reduction after this step.
Static Timing Analysis
This task usually starts with a placed and routed design, then generating a transistor level netlist for it and further optimizing it. Optimization can be for example adjusting transistor widths, or assigning different transistor threshold voltages in a dual threshold voltage design. This can be done algorithmically (e.g. TILOS) or in an ad-hoc fashion. See how much timing improvement you get vs. just gate-level optimization. Also notice any &qu…
Semiconductor Industry
Anuj, who's worked on video chips for nearly 20 years, is a great role model for all practicing engineers. He's worked in multiple successful startups, thrived through several acquisitions into some of the largest semiconductor makers, as well as had a stint in the public sector. He's even taken a foray into EDA for system design and managed to fit in a sabbatical. Through all this he has stayed a hands-on designer, managing co…
Static Timing Analysis
Updated 28 Aug 2023; expanded Nov 2026. Backend physical design interviews test whether you can take a synthesised netlist to a routed, timing-clean, power-clean and manufacturable layout, and explain the trade-offs at each step. Expect questions on the flow and its input and output files first, then floorplanning and power planning, placement, clock tree synthesis, routing, static timing, signal integrity, IR drop, electromigration and physic…
by
Murugavel Ganesan
May 19, 2010
Semiconductor Industry
Here are five of the most insulting leadership practices , the ones that virtually guarantee a business will end up with the most self-esteem challenged, optionless team members when the dust settles.
Synthesis
These nine RTL synthesis and backend interview questions cover the physical design topics interviewers return to most: parallelising the flow, reading timing reports, fixing violations, Elmore delay, wire sizing, zero-skew clock trees, in-place optimisation, ordering a clock and place-and-route flow, and design file sizes. Each question has the short answer an interviewer expects, followed by a fuller explanation. Several earlier explanations on…
