Synopsys

Pain Killers for the Fixed-Point Design Flow

Taking a floating-point representation of an algorithm into a fixed-point representation is an integral step on the path towards implementation. Unfortunately, it is known to be time-consuming, tedious and error prone. This paper from synopsys describes proven methodologies on how to overcome the hurdles, including many useful tips to get you to results faster.

Synopsys

Advanced On-Chip Variation (OCV) in PrimeTime

This application note from synopsys describes the advanced on-chip variation (OCV) solution in PrimeTime, including the recommended usage flow, and also provides an example script. The information described in this document is valid for PrimeTime versions starting with B-2008.12.

Synopsys

Design Compiler 2010 Doubles Productivity of Synthesis and Place-and-Route

Synopsys, Inc. has introduced Design Compiler 2010, the latest RTL synthesis innovation within the Galaxy™ Implementation platform, which delivers a two-fold speed-up in the synthesis and physical implementation flow. To meet aggressive schedules for increasingly complex designs, engineers need an RTL synthesis solution that enables them to minimize iterations to speed up physical implementation. To address these challenges, topographical tech…