Synchronization
Asynchronous in a synchronous world - Part 2
Performing static timing analysis is the process of verifying that every signal path in a design meets required clock-c…
Showing posts from December, 2005
Synchronization
Asynchronous in a synchronous world - Part 1
The purpose of synchronizing signals is to protect downstream logic from the metastable state of the first flip-flop in…
Synchronization
Asynchronous in a synchronous world - Introduction
I am composing this article to explore various aspects of clock and data synchronization. The first part of the article…
Coding
Verilog code to detect if a 64bit pattern can be expressed using power of 2
module pat_det ( data_in, patDetected ); input [31:0] data_in; output patDetected; wire [4:0] patSum = data_in[0] + dat…
Verilog
Verilog Shift Register with Test Bench
A Verilog module for a 4-bit shift register with a testbench. The shift register will be a simple serial-in, serial-ou…
Verilog
Verilog Awareness
Differentiate between Inter assignment Delay and Inertial Delay ? What are the different State machine Styles ? Which i…
Verilog
Verilog Awareness
Consider a 2:1 mux , what will be the output F if the Select (sel) is "X" ? What is the difference between bl…
Jitter
Clock Jitter
Clock jitter is the deviation from the ideal timing of clock transition events. Because such deviation can be detriment…
Verilog
Verilog Blocking Vs Non Blocking, Myths and Facts
I know people who swear by blocking and some who swear by non-blocking. So here are some thoughts. There is very little…
Synthesis
Clock tree synthesis
Basics of Clock Tree Synthesis: The main idea is to balance the skew between endpoints. They are built with the followi…
Guidelines
Design Guidelines and Criteria for Digital Electronics
..apparently these pages on guidelines and criteria, are from NASA. I think this is a very nice article with good amoun…
State Machines
"Safe" and "Unsafe" state machines
"Safe" State Machines: If the number of states (N) is a power of 2 and you use a binary or gray-code encoding…
Metastability
Metastability
Metastability in electronic circuits Metastability is a phenomenon that occurs in digital circuits when an input signal…
Interview Questions
Synthesizable Verilog from behavioral constructs - 5
Delay statements, e.g. @(posedge clock), require careful attention if there are several in a row. If there are only del…
Interview Questions
Synthesizable Verilog from behavioral constructs - 4
When implementing Verilog tasks in modules, the best approach is to group tasks that have the same output signals into …
Interview Questions
synthesizable Verilog from behavioral constructs - 3
To modify a behavioural Verilog fork and join statement to make it synthesizable. Behavioural: command1; fork //…
Interview Questions
synthesizable Verilog from behavioral constructs - 2
Modifying a behavioural Verilog while statement to make it synthesizable. Behavioural: command1; while (x != 0) …
Interview Questions
synthesizable Verilog from behavioral constructs - 1
Modifying a behavioural Verilog wait statement to make it synthesizable. Behavioural: command1; wait (x != 0); c…
Digital
A nice site for basics on Digital Logic Design
http://www.allaboutcircuits.com/ , Look up Volume IV - Digital Summary of topics covered... Chapter 1: NUMERATION SYS…
Learning
1's complement and 2's complement
In digital logic design, one of the ways to represent negative numbers is by using signed number representation. One of…
Setup
negative setup and hold time
A negative setup and hold condition is a very interesting proposition in static timing analysis. Support for this type …