Showing posts from December, 2005
Synchronization
Performing static timing analysis is the process of verifying that every signal path in a design meets required clock-cycle timing, whether or not all of the signal paths are even possible. Static timing analysis is not used to verify the functionality of the design, only that the design meets timing goals. In theory, timing verification could be accomplished by running exhaustive gatelevel simulations with SDF backannotation of actual timing va…
by
The Editor's Desk
December 23, 2005
Synchronization
The purpose of synchronizing signals is to protect downstream logic from the metastable state of the first flip-flop in a new clock domain. A simple synchronizer comprises two flip-flops in series without any combinational circuitry between them. This design ensures that the first flip-flop exits its metastable state and its output settles before the second flip-flop samples it.You also need to place the flipflops close to each other to ensure t…
by
The Editor's Desk
December 22, 2005
Synchronization
I am composing this article to explore various aspects of clock and data synchronization. The first part of the article talks about Level Synchronizers, Edge Synchronizers and Pulse Synchronizers. The second part deals with Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs. Applications, including disk-drive controllers, CDROM/DVD controllers, modems, network interfaces,and network processors, bear inherent challe…
by
The Editor's Desk
December 22, 2005
Coding
module pat_det ( data_in, patDetected ); input [31:0] data_in; output patDetected; wire [4:0] patSum = data_in[0] + data_in[1] + data_in[2] + data_in[3] + data_in[4] + data_in[5] + data_in[6] + data_in[7] + data_in[8] + data_in[9] + data_in[10] + data_in[11] + data_in[12] + data_in[13] + data_in[14] + data_in[15] + data_in[16] + data_in[17] + data_in[18] + data_in[19] + data_in[20] + data_in[20] + data_in[21] + data_in[22] + data_in[23] + data_i…
by
The Editor's Desk
December 21, 2005
Verilog
A Verilog module for a 4-bit shift register with a testbench. The shift register will be a simple serial-in, serial-out design with a clock, reset, and data input. module shift_register ( input wire clk, // Clock input input wire reset, // Synchronous reset input wire data_in, // Serial data input output reg data_out, // Serial data output output reg [3:0] reg_content // Current register content ); // …
by
The Editor's Desk
December 20, 2005
Verilog
Differentiate between Inter assignment Delay and Inertial Delay ? What are the different State machine Styles ? Which is better ? Why and when do we use one ove the other? Explain Disadv. and Adv.? What is the difference between the following lines of code ? reg1<= #10 reg2 ; reg3 = # 10 reg 4 ; What is value of Var1 after the following assignment ? reg Var1; initial begin Var1<= "-" end What…
by
The Editor's Desk
December 18, 2005
Verilog
Consider a 2:1 mux , what will be the output F if the Select (sel) is "X" ? What is the difference between blocking and nonblocking assignment? Explain with a simple example? What is the difference between wire and a reg data type? Write code for async reset D-Flip-Flop, Shift Register. Write code for 2:1 MUX using different coding styles. Write code for parallel encoder and priority encoder. Different "case" usage styles! Ex…
by
The Editor's Desk
December 18, 2005
Jitter
Clock jitter is the deviation from the ideal timing of clock transition events. Because such deviation can be detrimental to high-speed data transfer and can degrade performance, jitter must bekept to a minimum in a high-speed system. High-speed signaling is very sensitive to jitter. As signals toggle faster and faster, tighter restrictions fall on the signal transmitter and receiver. In many high-speed data applications, the clock edge must fal…
by
The Editor's Desk
December 18, 2005
Verilog
I know people who swear by blocking and some who swear by non-blocking. So here are some thoughts. There is very little difference between non-blocking and blocking in speed and no errors if done correctly either way. The main differences are: Some people like non-blocking because you can tell that a reg on the left hand side of /* example 1a */ reg a,b,c; always @(posedge clock) begin b /* b and c will be flip flops */…
by
The Editor's Desk
December 16, 2005
Synthesis
Basics of Clock Tree Synthesis: The main idea is to balance the skew between endpoints. They are built with the following constraints. Clock Skew: Difference between the clock arrival times. Clock Latency: Max delay between the clock root and clock leaf. Transition Time Clock buffers are usually bigger in size and have a shorter transition time as well as a more even rise and fall times. Clock nets are generally routed first and…
by
The Editor's Desk
December 16, 2005
Guidelines
..apparently these pages on guidelines and criteria, are from NASA. I think this is a very nice article with good amount discussion on critical aspects of Digital Design. http://klabs.org/DEI/References/design_guidelines/nasa_guidelines/clocks/clocks.htm
by
The Editor's Desk
December 14, 2005
State Machines
"Safe" State Machines: If the number of states (N) is a power of 2 and you use a binary or gray-code encoding algorithm, then the state machine is "safe." This ensures that you have M number of registers where N = 2M. Because all of the possible state values (or register statuses) are reachable, the design is "safe." "Unsafe" State Machines: If the number of states is not a power of 2, or if you do not use…
by
The Editor's Desk
December 13, 2005
Metastability
Metastability in electronic circuits Metastability is a phenomenon that occurs in digital circuits when an input signal changes near the edge of a clock pulse. This can cause the output of a flip-flop or a latch to enter an undefined state, where it is neither high nor low, but somewhere in between. This state can persist for an unpredictable amount of time, until the output settles to a stable value. This can lead to errors and glitches in the …
by
The Editor's Desk
December 13, 2005
Interview Questions
Delay statements, e.g. @(posedge clock), require careful attention if there are several in a row. If there are only delays on the positive edge of the clock you can implement them with a state machine: Behavioural: forever begin command1; @(posedge clock); command2; @(posedge clock); command3; @(posedge clock); end Synthesizable: always @(posedge clock or posedge reset) if (reset) // reset the state machine when reset is high b…
by
The Editor's Desk
December 13, 2005
Interview Questions
When implementing Verilog tasks in modules, the best approach is to group tasks that have the same output signals into separate modules. If different modules control the same signal, then explicit arbitration logic is required to specify which module is controlling the signal at a given time. To put tasks in a separate module, you will require start and completion handshaking signals. Behavioural: task update_a_and_b; begin a = y; wait (z…
by
The Editor's Desk
December 13, 2005
Interview Questions
To modify a behavioural Verilog fork and join statement to make it synthesizable. Behavioural: command1; fork // start of fork block 1 begin wait (y != 0); a = y; end // start of fork block 2 begin wait (z != 0); b = z; end join command2; command2 will execute only after fork blocks 1 and 2 have finished. Synthesizable: case (state) 0 : begin command1; done_fork_block_1 = 0; done_fork_block_2 = 0; if (y != 0) begi…
by
The Editor's Desk
December 13, 2005
Interview Questions
Modifying a behavioural Verilog while statement to make it synthesizable. Behavioural: command1; while (x != 0) begin command2; end command3; Synthesizable: case (state) 0 : begin command1; if (x != 0) begin command2; state <= 1; end else command3; end 1 : if (x != 0) begin command2; end else command3; endcase Again, if a cycle delay between command1 and the other commands executing is acceptable, simpler code …
by
The Editor's Desk
December 13, 2005
Interview Questions
Modifying a behavioural Verilog wait statement to make it synthesizable. Behavioural: command1; wait (x != 0); command3; Synthesizable: case (state) 0 : begin command1; if (x != 0) command3; else state <= 1; end 1 : if (x != 0) // wait until this is true command3; endcase You also need to add the variable state, reg state. If a cycle delay between command1 and command3 does not matter, then the following is simpler, but …
by
The Editor's Desk
December 13, 2005
Digital
http://www.allaboutcircuits.com/ , Look up Volume IV - Digital Summary of topics covered... Chapter 1: NUMERATION SYSTEMS Chapter 2: BINARY ARITHMETIC Chapter 3: LOGIC GATES Chapter 4: SWITCHES Chapter 5: ELECTROMECHANICAL RELAYS Chapter 6: LADDER LOGIC Chapter 7: BOOLEAN ALGEBRA Chapter 8: KARNAUGH MAPPING Chapter 9: COMBINATIONAL LOGIC FUNCTIONS Chapter 10: MULTIVIBRATORS Chapter 11: COUNTERS Chapter 12: SHIFT RE…
by
The Editor's Desk
December 10, 2005
Learning
In digital logic design, one of the ways to represent negative numbers is by using signed number representation. One of the commonly used signed number representation methods is 2's complement, while the other is 1's complement. Here are the differences between the two: 1's Complement: In 1's complement, negative numbers are represented by taking the bitwise complement of the corresponding positive number. For example, to repres…
by
The Editor's Desk
December 07, 2005
Setup
A negative setup and hold condition is a very interesting proposition in static timing analysis. Support for this type of conditions was added in the Verilog LRM, only in the late 90's (using the $SETUP and $HOLD constructs). The basic idea is something like this: Consider a module with an ideal flop in it. Now, there exists a data path (from primary inputs of module to D of flop) and a clock path (from primary inputs to CLK of flop). Suppos…
by
The Editor's Desk
December 07, 2005
